LTC3567 datasheet(14/28 Pages) LINER

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LTC3567

3567f

OPERATION

chip P-channel MOSFET transistor whenever the voltage at

VOUT is approximately 15mV (VFWD) below the voltage at

BAT. The resistance of the internal ideal diode is approxi-

mately 180mΩ. If this is sufﬁcient for the application, then

no external components are necessary. However, if more

conductance is needed, an external P-channel MOSFET

transistor can be added from BAT to VOUT.

When an external P-channel MOSFET transistor is present,

the GATE pin of the LTC3567 drives its gate for automatic

ideal diode control. The source of the external P-chan-

nel MOSFET should be connected to VOUT and the drain

should be connected to BAT. Capable of driving a 1nF load,

the GATE pin can control an external P-channel MOSFET

transistor having an on-resistance of 40mΩ or lower.

Suspend LDO

If the LTC3567 is conﬁgured for USB suspend mode, the

switching regulator is disabled and the suspend LDO

provides power to the VOUT pin (presuming there is power

available to VBUS). This LDO will prevent the battery from

running down when the portable product has access to

a suspended USB port. Regulating at 4.6V, this LDO only

becomes active when the switching converter is disabled

(suspended). To remain compliant with the USB speciﬁca-

tion, the input to the LDO is current limited so that it will

not exceed the 500μA low power suspend speciﬁcation.

If the load on VOUT exceeds the suspend current limit,

the additional current will come from the battery via the

ideal diode.

3.3V Always-On Supply

The LTC3567 includes a low quiescent current low drop-out

regulator that is always powered. This LDO can be used to

provide power to a system pushbutton controller, standby

microcontroller or real time clock. Designed to deliver up

to 25mA, the always-on LDO requires at least a 1μF low

impedance ceramic bypass capacitor for compensation.

The LDO is powered from VOUT, and therefore will enter

dropout at loads less than 25mA as VOUT falls near 3.3V.

If the LDO3V3 output is not used, it should be disabled

by connecting it to VOUT.

VBUS Undervoltage Lockout (UVLO)

An internal undervoltage lockout circuit monitors VBUS and

keeps the PowerPath switching regulator off until VBUS

rises above 4.30V and is at least 200mV above the battery

voltage. Hysteresis on the UVLO turns off the regulator if

VBUS drops below 4.00V or to within 50mV of BAT. When

this happens, system power at VOUT will be drawn from

the battery via the ideal diode.

Figure 3. PowerPath Block Diagram

–

0.3V

1.206V

3.6V

CLPROG

ISWITCH/N

+ –

15mV

IDEAL

DIODE

PWM AND

GATE DRIVE

AVERAGE INPUT

CURRENT LIMIT

CONTROLLER

AVERAGE OUTPUT

VOLTAGE LIMIT

CONTROLLER

CONSTANT CURRENT

CONSTANT VOLTAGE

BATTERY CHARGER

GATE

VOUT

3.5V TO

(BAT + 0.3V)

TO SYSTEM

LOAD

OPTIONAL

EXTERNAL

IDEAL DIODE

PMOS

SINGLE CELL

Li-Ion

3567 F03

BAT

VBUS

TO USB

OR WALL

ADAPTER

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