LTC3670

6

3670f

PIN FUNCTIONS

BLOCK DIAGRAM

SW (Pin 1): Buck Regulator Switch Node Connection to In-

ductor. This pin connects to the drains of the buck regulator’s

main PMOS and synchronous NMOS switches.

GND (Pin 2): Ground.

ENLDO1 (Pin 3): Enables the First Low Dropout Linear

Regulator (LDO1) When High. This is a MOS gate input.

There is an internal 4MΩ pull-down.

ENLDO2 (Pin 4): Enables the Second Low Dropout Linear

Regulator (LDO2) When High. This is a MOS gate input.

There is an internal 4MΩ pull-down.

ENBUCK (Pin 5): Enables the Buck Converter When High.

This is a MOS gate input. There is an internal 4MΩ pull-

down.

BUCKFB (Pin 6): Feedback Voltage Input for the Buck

Regulator. Typically, an external resistor divider feeds a

fraction of the buck output voltage to this pin.

PGOOD (Pin 7): Power Good Open-Drain NMOS Output.

The PGOOD pin goes Hi-Z when all enabled outputs are

within 8% of final value.

LDO2_FB (Pin 8): Feedback Voltage Input for the Second

Low Dropout Linear Regulator (LDO2). Typically, an ex-

ternal resistor divider feeds a fraction of the LDO2 output

voltage to this pin.

LDO1_FB (Pin 9): Feedback Voltage Input for the First Low

Dropout Linear Regulator (LDO1). Typically, an external

resistor divider feeds a fraction of the LDO1 output volt-

age to this pin.

LDO1 (Pin 10): Output of the First Low Dropout Linear

Regulator. This pin must be bypassed to ground with a

1μF or greater ceramic capacitor.

LDO2 (Pin 11): Output of the Second Low Dropout Linear

Regulator. This pin must be bypassed to ground with a

1μF or greater ceramic capacitor.

to ground with a 2.2μF or greater ceramic capacitor.

Exposed Pad (Pin 13): Ground. This pin must be soldered

to the PCB.

400mA BUCK

2

GND

3

ENLDO1

6

BUCKFB

4

ENLDO2

5

ENBUCK

ENABLE

BUCK

12

SW

2.25MHz

OSC

LOGIC

LDO2_FB

3670 BD

LDO1_FB

PGOOD

13

GND

800mV

REFERENCE

ENABLE_LDO2

ENABLE_LDO1

POWER GOOD

COMPARATORS

7

LDO1

10

LDO2

11

9

8

1

LDO2

LDO1