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LTC3813

3813fb

Power MOSFET Selection

The LTC3813 requires two external N-channel power

MOSFETs, one for the bottom (main) switch and one for

the top (synchronous) switch. Important parameters for

the power MOSFETs are the breakdown voltage BVDSS,

threshold voltage V(GS)TH, on-resistance RDS(ON), Miller

capacitance and maximum current IDS(MAX).

When the bottom MOSFET is used as the current sense

element, particular attention must be paid to its on-resis-

tance. MOSFET on-resistance is typically speciﬁed with

a maximum value RDS(ON)(MAX) at 25°C. In this case,

additional margin is required to accommodate the rise in

MOSFET on-resistance with temperature:

RDS(ON)(MAX) =

RSENSE

The

ρT term is a normalization factor (unity at 25°C)

accounting for the signiﬁcant variation in on-resistance

with temperature (see Figure 2) and typically varies

from 0.4%/°C to 1.0%/°C depending on the particular

MOSFET used.

The most important parameter in high voltage applications

is breakdown voltage BVDSS. Both the top and bottom

MOSFETs will see full output voltage plus any additional

ringing on the switch node across its drain-to-source dur-

ing its off-time and must be chosen with the appropriate

breakdown speciﬁcation. Since most MOSFETs in the 60V

to 100V range have higher thresholds (typically VGS(MIN)

≥ 6V), the LTC3813 is designed to be used with a 6.2V to

14V gate drive supply (DRVCC pin).

For maximum efﬁciency, on-resistance RDS(ON) and input

capacitance should be minimized. Low RDS(ON) minimizes

conduction losses and low input capacitance minimizes

transition losses. MOSFET input capacitance is a combi-

nation of several components but can be taken from the

typical “gate charge” curve included on most data sheets

(Figure 3).

Figure 3. Gate Charge Characteristic

The curve is generated by forcing a constant input cur-

rent into the gate of a common source, current source

loaded stage and then plotting the gate voltage versus

time. The initial slope is the effect of the gate-to-source

and the gate-to-drain capacitance. The ﬂat portion of the

curve is the result of the Miller multiplication effect of the

drain-to-gate capacitance as the drain drops the voltage

across the current source load. The upper sloping line is

due to the drain-to-gate accumulation capacitance and

the gate-to-source capacitance. The Miller charge (the

APPLICATIONS INFORMATION

Figure 2. RDS(ON) vs Temperature

JUNCTION TEMPERATURE (°C)

–50

1.0

1.5

150

3813 F02

0.5

100

2.0

–

VDS

VOUT

VGS

MILLER EFFECT

QIN

CMILLER = (QB – QA)/VDS

VGS

–

3813 F03

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