CDC857-2, CDC857-3

2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

SCAS627A – SEPTEMBER 1999 – DECEMBER 1999

8

POST OFFICE BOX 655303

APPLICATION EXAMPLE

SDRAM

Stack

≈ 2.5”

≈ 0.6” (Split to Terminator)

0.3”

120

Ω

SDRAM

Stack

VTR

VCP

SDRAM represents

a capacitive load

PLL

CLK

CLK

120

Ω

16 pF

120

Ω

16 pF

FBIN

FBIN

Figure 2. Clock Structure #2

differential clock signals

Figure 3 shows the differential clocks are directly terminated by a 120-

Ω resistor.

Receiver

60

Ω

60

Ω

RT = 120 Ω

VCC

OUT

OUT

Device

Under

Test

VCC

VTR

VCP

Figure 3. Differential Signal Using Direct Termination Resistor