PCI1225PDV datasheet(39/131 Pages) TI

39 / 131 page

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MAY 1998 – REVISED – MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

using parallel IRQ interrupts (continued)

As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10,

IRQ11, and IRQ15. The multifunction control register must be programmed to a value of 0x0FBA5432. This

value routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in

Figure 16. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some

circuitry that provides parallel PCI interrupts to the host.

PCI1225

PIC

MFUNC1

MFUNC2

MFUNC3

MFUNC4

MFUNC5

MFUNC6

IRQ3

IRQ4

IRQ5

IRQ10

IRQ11

IRQ15

Figure 16. IRQ Implementation

Power-on software is responsible for programming the multifunction routing register to reflect the IRQ

configuration of a system implementing the PCI1225. The multifunction routing register is shared between the

two PCI1225 functions, and only one write to function 0 or 1 is necessary to configure the MFUNC6:0 signals.

Writing to only function 0 is recommended. See the

multifunction routing register description on page 64 for

details on configuring the multifunction terminals.

The parallel ISA type IRQ signaling from the MFUNC6:0 terminals is compatible with those input directly into

the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design

constraints may demand more MFUNC6:0 IRQ terminals than the PCI1225 makes available. A system designer

may choose to implement an IRQSER deserializer companion chip, such as the Texas Instruments PCI950.

To use a deserializer, the MFUNC3 terminal must be configured as IRQSER and connected to the deserializer,

which outputs all 15 ISA IRQs and four PCI interrupts as decoded from the IRQSER stream.

using parallel PCI interrupts

Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode parallel ISA IRQ signaling

mode, and when only IRQs are serialized with the IRQSER protocol. Both INTA and INTB can be routed to

MFUNC terminals (MFUNC0 and MFUNC1). However, interrupts of both socket functions can be routed to INTA

(MFUNC0) if the INTRTIE bit is set in the system control register.

The INTRTIE bit effects the read-only value provided through accesses to the interrupt pin register. When

INTRTIE bit is set, both functions return a value of 0x01 on reads from the interrupt pin register for both parallel

and serial PCI interrupts. The interrupt signalling modes are summarized in Table 15.

PCI1225PDV Datasheet(PDF) 39 Page - Texas Instruments

PCI1225PDV Datasheet(HTML) 39 Page - Texas Instruments

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