PCI1410 datasheet(51/145 Pages) TI

51 / 145 page

3–17

The

1997 PC Card Standard describes the power-up sequence that must be followed by the PCI1410 when an

insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this

power-up sequence, the PCI1410 interrupt scheme can be used to notify the host system (see Table 3–9), denoted

by the power cycle complete event. This interrupt source is considered a PCI1410 internal event because it depends

on the completion of applying power to the socket rather than on a signal change at the PC Card interface.

3.7.2

Interrupt Masks and Flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3–9 by setting

the appropriate bits in the PCI1410. By individually masking the interrupt sources listed, software can control those

events that cause a PCI1410 interrupt. Host software has some control over the system interrupt the PCI1410 asserts

by programming the appropriate routing registers. The PCI1410 allows host software to route PC Card CSC and PC

Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling

method used is discussed in more detail in the following sections.

When an interrupt is signaled by the PCI1410, the interrupt service routine must determine which of the events listed

in Table 3–8 caused the interrupt. Internal registers in the PCI1410 provide flags that report the source of an interrupt.

By reading these status bits, the interrupt service routine can determine the action to be taken.

Table 3–8 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can

be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Notice that there is not a mask bit to stop the PCI1410 from passing PC Card functional interrupts through to the

appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never

be a card interrupt that does not require service after proper initialization.

Table 3–8 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC

Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the

flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2

(IFCMODE) in the ExCA global control register (see Section 5.20), located at ExCA offset 1Eh/81Eh, and defaults

to the

flag cleared on read method.

The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket force event

registers, software should not program the chip through both register sets when a CardBus card is functioning.

3.7.3

Using Parallel IRQ Interrupts

The seven multifunction terminals, MFUNC6–MFUNC0, implemented in the PCI1410 may be routed to obtain a

subset of the ISA IRQs . The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel

ISA type IRQ interrupt signaling, software must program the device control register (offset 92h, see Section 4.33),

located at PCI offset 92h, to select the parallel IRQ signaling scheme. See Section 4.30,

Multifunction Routing

A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement

is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal

for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.

As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11,

and IRQ15. The multifunction routing register must be programmed to a value of 0FBA 5432h. This value routes the

MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3–16. Not shown is

that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel

PCI interrupts to the host.

PCI1410 Datasheet(PDF) 51 Page - Texas Instruments

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