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EP4SE290 Datasheet(PDF) 13 Page - Altera Corporation |
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EP4SE290 Datasheet(HTML) 13 Page - Altera Corporation |
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13 / 40 page  Chapter 1: DC and Switching Characteristics 1–11 Switching Characteristics © December 2008 Altera Corporation Stratix IV Device Handbook, Volume 4 Table 1–19. Stratix IV GX Transceiver Specification (Part 1 of 4) Symbol/ Description Conditions -2 Speed Commercial Speed Grade -3 Commercial/Industrial and -2x Commercial Speed Grade (1) -4 Speed Commercial Speed Grade Unit Min Typ Max Min Typ Max Min Typ Max Reference Clock Input frequency from REFCLK input pins — 50 — 637.5 50 — 637.5 50 — 622.08 MHz Phase frequency detector (CMU PLL and receiver CDR) — 50 — 425 50 — 325 50 — 325 MHz Absolute VMAX for a REFCLK pin —— — 1.6 — — 1.6 — — 1.6 V Operational VMAX for a REFCLK pin —— — 1.5 — — 1.5 — — 1.5 V Absolute VMIN for a REFCLK pin — -0.3 — — -0.3 — — -0.3 — — V Rise/fall time — — — 0.2 — — 0.2 — — 0.2 UI Duty cycle — 45 — 55 45 — 55 45 — 55 % Peak-to-peak differential input voltage — 200 — 1600 200 — 1600 200 — 1600 mV Spread-spectrum modulating clock frequency PCI Express 30 — 33 30 — 33 30 — 33 kHz Spread-spectrum downspread PCI Express — 0 to -0.5% —— 0 to -0.5% —— 0 to -0.5% —— On-chip termination resistors — — 100 — — 100 — — 100 — Ω VICM (AC coupled) — — 1100 — — 1100 — — 1100 — mV VICM (DC coupled) HCSL I/O standard for PCI Express reference clock 250 — 550 250 — 550 250 — 550 mV RREF — — — 2000 ± 1% — — 2000 ± 1% — — 2000 ± 1% — Ω Transceiver Clocks Calibration block clock frequency — 10 — 125 10 — 125 10 — 125 MHz fixedclk clock frequency PCI Express Receiver Detect — 125 — — 125 — — 125 — MHz reconfig_clk clock frequency Dynamic reconfiguration clock frequency 2.5/ 37.5 (2) —50 2.5/ 37.5 (2) —50 2.5/ 37.5 (2) —50 — |
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