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LTC2222/LTC2223

22223fa

Data Format

The LTC2222/LTC2223 parallel digital output can be se-

lected for offset binary or 2’s complement format. The

format is selected with the MODE pin. Connecting MODE

to GND or 1/3VDD selects offset binary output format.

Connecting MODE to 2/3VDD or VDD selects 2’s comple-

ment output format. An external resistor divider can be

used to set the 1/3VDD or 2/3VDD logic values. Table 2

shows the logic states for the MODE pin.

Overflow Bit

When OF outputs a logic high the converter is either

overranged or underranged.

Output Clock

The ADC has a delayed version of the ENC+ input available

as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system. This

is necessary when using a sinusoidal encode. Data will be

updated just after CLKOUT rises and can be latched on the

falling edge of CLKOUT.

APPLICATIO S I FOR ATIO

Table 2. MODE Pin Function

Clock Duty

MODE Pin

Output Format

Cycle Stablizer

Offset Binary

Off

1/3VDD

Offset Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

example if the converter is driving a DSP powered by a 1.8V

supply then OVDD should be tied to that same 1.8V supply.

OVDD can be powered with any voltage up to 3.6V. OGND

can be powered with any voltage from GND up to 1V and

must be less than OVDD. The logic outputs will swing be-

tween OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin, OE.

OE high disables all data outputs including OF and CLKOUT.

The data access and bus relinquish times are too slow to

allow the outputs to be enabled and disabled during full

speed operation. The output Hi-Z state is intended for use

during long periods of inactivity.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normal operation. Connecting SHDN to VDD and OE to VDD

results in sleep mode, which powers down all circuitry

including the reference and typically dissipates 1mW. When

exiting sleep mode it will take milliseconds for the output

data to become valid because the reference capacitors have

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