SN75ALS197

QUADRUPLE DIFFERENTIAL LINE RECEIVER

SLLS045B – JANUARY 1989 – REVISED MAY 1995

4

POST OFFICE BOX 655303

electrical characteristics over recommended range of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIT+

Positive-going input threshold voltage

300

mV

VIT–

Negative-going input threshold voltage

– 300‡

mV

Vhys

Hysteresis voltage (VIT+ – VIT –)

See Figure 4

120

mV

VIK

Enable-input clamp voltage

II = –18 mA

– 1.5

V

VOH

High-level output voltage

VID = 300 mV,

IOH = – 400 µA

2.7

3.6

V

VOL

Low level output voltage

VID = 300 mV

IOL = 8 mA

0.45

V

VOL

Low-level output voltage

VID = – 300 mV

IOL = 16 mA

0.5

V

IOZ

High impedance state output current

VCC = 5 25 V

VO = 2.4 V

20

µA

IOZ

High-impedance-state output current

VCC = 5.25 V

VOH = 0.4 V

–20

µA

II

Line input current

Other input at 0 V,

VI = 15 V

0.7

1.2

mA

II

Line input current

,

See Note 3

VI = –15 V

– 1.0

– 1.7

mA

IH

High level enable input current

VIH = 2.7 V

20

µA

IH

High-level enable-input current

VIH = 5.25 V

100

µA

IIL

Low-level enable-input current

VIL = 0.4 V

– 100

µA

Input resistance

12

18

k

Ω

IOS

Short-circuit output current§

VID = 3 V,

VO = 0

–15

–78

– 130

mA

ICC

Supply current

Outputs disabled

22

35

mA

† All typical values are at VCC = 5 V, TA = 25°C.

‡ The algebraic convention, in which the less positive limit is designated minimum, is used in this data sheet for threshold voltage levels only.

§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

NOTE 3: Refer to ANSI Standard EIA/TIA-422-B and EIA/TIA-423-B for exact conditions.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH

Propagation delay time, low- to high-level output

VID = – 2.5 V to 2.5 V,

CL = 15 pF,

15

22

ns

tPHL

Propagation delay time, high- to low-level output

ID

,

See Figure 2

L

,

15

22

ns

tPZH

Output enable time to high level

CL =15 pF

See Figure 3

13

25

ns

tPZL

Output enable time to low level

CL = 15 pF,

See Figure 3

11

25

ns

tPHZ

Output disable time from high level

CL =15 pF

See Figure 3

13

25

ns

tPLZ

Output disable time from low level

CL = 15 pF,

See Figure 3

15

22

ns