SN75ALS197

QUADRUPLE DIFFERENTIAL LINE RECEIVER

SLLS045B – JANUARY 1989 – REVISED MAY 1995

2

POST OFFICE BOX 655303

1A

2

1B

1

2A

6

2B

7

3A

10

3B

9

4A

14

4B

15

3

1Y

5

2Y

11

3Y

13

4Y

4

G

12

G

EN

≥ 1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

logic diagram (positive logic)

4Y

3Y

2Y

1Y

13

11

5

3

4

4B

4A

3B

3A

2B

2A

1B

1A

15

14

9

10

7

6

1

2

12

G

G

schematics of inputs and outputs

EQUIVALENT OF EACH A OR B INPUT

EQUIVALENT OF G OR G INPUTS

EQUIVALENT OF ALL OUTPUTS

GND

VCC

Input

VCC

VCC

Input

GND

3 k

Ω

NOM

18 k

Ω

NOM

300 k

Ω

NOM

2 k

Ω

NOM

VCC (A)

or

GND (B)

GND

22 k

Ω

NOM

Output

50 k

Ω

NOM