TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MAY 1999

22

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Each register is selected using it’s own combination of address lines A[0], A[1], A[2]. The programming

combinations for register selection are shown in Table 7.

Table 7. Register Map – Read/Write Properties

A[2]

A[1]

A[0]

READ MODE

WRITE MODE

0

0

0

Receive holding register (RHR)

Transmit holding register (THR)

0

0

1

Interrupt enable register (IER)

Interrupt enable register

0

1

0

Interrupt identification register (IIR)

FIFO control register (FCR)

0

1

1

Line control register (LCR)

Line control register

1

0

0

Modem control register (MCR)

Modem control register

1

0

1

Line status register (LSR)

1

1

0

Modem status register (MSR)

1

1

1

Scratch register (SPR)

Scratch register (SPR)

0

0

0

Divisor latch LSB (DLL)

Divisor latch LSB (DLL)

0

0

1

Divisor latch MSB (DLH)

Divisor latch MSB (DLH

0

1

0

Enhanced feature register (EFR)

Enhanced feature register

1

0

0

Xon-1 word

Xon-1 word

1

0

1

Xon-2 word

Xon-2 word

1

1

0

Xoff-1 word

Xoff-1 word

1

1

1

Xoff-2 word

Xoff-2 word

1

1

0

Transmission control register (TCR)

Transmission control register

1

1

1

Trigger level register (TLR)

Trigger level register

1

1

1

FIFO ready register

† DLL and DLH are accessible only when LCR bit-7, is 1.

Enhanced feature register, Xon1, 2 and Xoff1, 2 are accessible only when LCR is set to 10111111 (8hBF).

Transmission control register and trigger level register are accessible only when EFR[4] = 1 and MCR[6] = 1, i.e.. EFR[4] and MCR[6] are

read/write enables.

FIFORdy register is accessible only when CSA and CSB = 0, MCR [bit 2] = 1 and loopback is disabled.