TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MAY 1999

3

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

IOW

15

I

Write input (active low strobe). A high to low transition on IOW will transfer the contents of the data bus (D0–D7)

from the external CPU to an internal register that is defined by address bits A0–A2 and CSA and CSB

OPA, OPB

32, 9

0

User defined outputs. This function is associated with individual channels A and B. The state at these pins is

defined by the user and through the software settings of the MCR register, bit 3. INTA–B are set to active mode

and OP to a logic 0 when the MCR–3 is set to a logic 1. INTA–B are set to the thru state mode and OP is set

to a logic 0. See bit 3, Modem Control Register (MCR bit 3).

RESET

36

I

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the

receiver input will be disabled during reset time. See TL16C752 external reset conditions for initialization

details.

RIA, RIB

41, 21

I

Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic 0 on

these pins indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on

these input pins generates an interrupt.

RTSA, RTSB

33, 22

O

Request to send (active low). These outputs are associated with individual UART channels A and B. A logic

0 on the RTS pins indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control

register (MCR bit 1) sets these pins to 0, indicating data is available. After a reset, these pins are set to 1. These

pins only affects the transmit and receive operation when auto RTS function is enabled through the enhanced

feature register (EFR) bit 6, for hardware flow control operation.

RXA, RXB

5, 4

I

Receive data input. These inputs are associated with individual serial channel data to the 752. During the local

loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX input

internally.

RXRDYA,

RXRDYB

31, 18

O

Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a timeout

interrupt occurs. They goes high when the RX FIFO is empty and there is an error in RX FIFO.

TXA, TXB

7, 8

O

Transmit data. These outputs are associated with individual serial transmit channel data from the 752. During

the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.

TXRDYA,

TXRDYB

43, 6

O

Transmit ready (active low). TXRDY A and B go low when there trigger level numbers of spares available. They

go high when the TX buffer is full.

VCC

42

I

Power supply inputs.

XTAL1

13

I

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can

be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figures 9 and 10).

Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.

XTAL2

14

O

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output

or buffered a clock output.