TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MAY 1999

26

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

line status register (LSR)

Table 11 shows line status register bit settings.

Table 11. Line Status Register (LSR) Bit Settings

BIT NO.

BIT SETTINGS

0

0 = No data in the receive FIFO

1 = At least one character in the RX FIFO

1

0 = No overrun error

1 = Overrun error has occurred.

2

0 = No parity error in data being read from RX FIFO

1 = Parity error in data being read from RX FIFO.

3

0 = No framing error in data being read from RX FIFO

1 = Framing error occurred in data being read from RX FIFO (i.e., received data did not have a valid stop bit)

4

0 = No break condition

1 = A break was detected while the data being read from the RX FIFO was being received. (i.e., RX i/p was low for one character

time frame).

5

0 = Transmit hold register is NOT empty

1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is enabled.

6

0 = Transmitter hold AND shift registers are not empty.

1 = Transmitter hold AND shift registers are empty.

7

0 = Normal operation

1 = At least one parity error, framing error or break indication in the receiver FIFO. BIt 7 is cleared when no more errors are present

in the FIFO.

When the LSR is read, LSR[4:2] reflect the error bits [BI, FE, PE] of the character at the top of the RX FIFO (next

character to be read). The LSR[4:2] registers don’t physically exist as the data read from the RX FIFO is output

directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore errors in a character are identified

by reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors

remaining in the FIFO.

NOTE:

Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read

pointer is incremented by reading the RHR. Reading the RX FIFO when it is empty could cause

LSR[7] to be set, which can only be reset by clearing the RX FIFO via FCR[1]. It is strongly

recommended that the RX FIFO be read only when data is present.