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TL16C752 Datasheet(PDF) 23 Page - Texas Instruments |
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TL16C752 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 33 page  TL16C752 3.3-V DUAL UART WITH 64-BYTE FIFO SLLS305 – MAY 1999 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION Table 8 lists and describes the TL16C752 internal registers. Table 8. TL16C752A Internal Registers Addr REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 READ/ WRITE 000 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read 000 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Write 001 IER 0/CTS interrupt enable† 0/RTS interrupt enable† 0/Xoff sleep mode† 0/X Sleep mode† Modem status interrupt Rx line status interrupt THR empty interrupt Rx data available interrupt Read/Write 010 FCR Rx trigger level Rx trigger level 0/TX trigger level† 0/TX trigger level† DMA mode select Resets Tx FIFO Resets Rx FIFO Enables FIFOs Write 010 IIR FCR(0) FCR(0) 0/CTS, RTS† 0/Xoff† Interrupt priority Bit 2 Interrupt priority Bit 1 Interrupt priority Bit 0 Interrupt status Read 011 LCR DLAB and EFR enable Break control bit Sets parity Parity type select Parity enable No. of stop bits Word length Word length Read/Write 100 MCR 1x or 1x/4 clock TCR and TLR enable 0/Xon Any 0/Enable loopback IRQ enable FIFO Rdy enable RTS DTR Read/Write 101 LSR 0/Error in Rx FIFO THR and TSR empty THR empty Break interrupt Framing error Parity error Over-run error Data in receiver Read 110 MSR CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS Read 111 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 000 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 001 DLH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Read/Write 010 EFR Auto-CTS Auto-RTS Special character detect Enable enhanced functions† S/W flow control Bit 3 S/W flow control Bit 2 S/W flow control Bit 1 S/W flow control Bit 0 Read/Write 100 Xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 101 Xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 110 Xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 111 Xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 110 TCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 111 TLR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read/Write 111 FIFO Rdy 0 0 RX FIFO B status RX FIFO A status 0 0 TX FIFO B status TX FIFO A status Read † The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled. |
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