TLC320AC02C datasheet(73/84 Pages) TI

73 / 84 page

B–1

Appendix B

Secondary Communications

The function of the control bits DS15 and DS14 and the hardware terminals FC0 and FC1 are shown below.

Any combinational state of DS15, DS14, FC1, and FC0 not shown is ignored.

CONTROL FUNCTION OF SECONDARY COMMUNICATION

BITS

TERMINALS

DS15

DS14

FC1

FC0

Ignored

On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

Ignored

On the next falling edge of the FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of DS15 and DS14 such that on the

next rising edge of FS, the next ADC/DAC sampling time occurs later by the number

of MCLK periods determined by the value contained in the A

′ register. When the A′

Ignored

On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of D01 and D00. On the next rising

edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK

periods determined by the value contained in the A

′ register. When the A′ register

value is negative, FS occurs later.

On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

On the next falling edge of the FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of FC1 and FC0 such that on the

next rising edge of FS, the next ADC/DAC sampling time occurs later by the number

of MCLK periods determined by the value contained in the A

′ register. When the A′

On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

The phase adjustment is determined by the state of FC1 and FC0 such that on the

next rising edge of FS, the next ADC/DAC sampling time occurs earlier by the number

of MCLK periods determined by the value contained in the A

′ register. When the A′

On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and

transmits the ADC data D15 – D00 from DOUT.

TLC320AC02C Datasheet(PDF) 73 Page - Texas Instruments

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