TLC320AC02C datasheet(12/84 Pages) TI

12 / 84 page

1–5

1.4

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.†

NO.‡

I/O

DESCRIPTION

ADC VDD

Analog supply voltage for the ADC channel

ADC VMID

Midsupply for the ADC channel (requires a bypass capacitor). ADC VMID must be

buffered when used as an external reference.

ADC GND

Analog ground for the ADC channel

AUX IN +

Noninverting input to auxiliary analog input amplifier

AUX IN –

Inverting input to auxiliary analog input amplifier

DAC VDD

Digital supply voltage for the DAC channel

DAC VMID

Midsupply for the DAC channel (requires a bypass capacitor). DAC VMID must be

buffered when used as an external reference.

DAC GND

Analog ground for the DAC channel

DIN

Data input. DIN receives the DAC input data and command information and is

synchronized with SCLK.

DOUT

Data output. DOUT outputs the ADC data results and register read contents.

DOUT is synchronized with SCLK.

DGTL VDD

Digital supply voltage for control logic

DGTL GND

Digital ground for control logic

EOC

End-of-conversion output. EOC goes high at the start of the ADC conversion

period and low when conversion is complete. EOC remains low until the next ADC

conversion period begins and indicates the internal device conversion period.

FC0

Hardware control input. FC0 is used in conjunction with FC1 to request secondary

communication and phase adjustments. FC0 should be tied low if it is not used.

FC1

Hardware control input. FC1 is used in conjunction with FC0 to request secondary

communication and phase adjustments. FC1 should be tied low if it is not used.

I/O

Frame synchronization. When FS goes low, DIN begins receiving data bits and

DOUT begins transmitting data bits. In master mode, FS is low during the

simultaneous 16-bit transmission to DIN and from DOUT. In slave mode, FS is

externally generated and must be low for one shift-clock period minimum to initiate

the data transfer.

FSD

Frame-synchronization delayed output. This active-low output synchronizes a

slave device to the frame synchronization timing of the master device. FSD is

applied to the slave FS input and is the same duration as the master FS signal but

delayed in time by the number of shift clocks programmed in the FSD register.

IN +

Noninverting input to analog input amplifier

IN –

Inverting input to analog input amplifier

MCLK

The master-clock input drives all the key logic signals of the AIC.

MON OUT

The monitor output allows monitoring of analog input and is a high-impedance

output.

M/S

Master/slave select input. When M/S is high, the device is the master and when

low, it is a slave.

† Terminal numbers shown are for the FN package.

‡ Terminal numbers shown are for the PM package.

TLC320AC02C Datasheet(PDF) 12 Page - Texas Instruments

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