TLC320AC02C datasheet(19/84 Pages) TI

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2–4

2.3

Master-Slave Terminal Function

Table 2–1 describes the function of the master/slave (M/S) input. The only difference between master and

slave operations in the TLC320AC02 is that SCLK and FS are outputs when M/S is high and inputs when

M/S is low.

Table 2–1. Master-Slave Selection

MODE

M/S†

SCLK

Master and Stand Alone

Output

Slave and Codec Emulation

Input

† When the stand-alone mode is desired or when the device is

permanently in the master mode, M/S must be high.

2.4

ADC Signal Channel

To produce excellent common-mode rejection of unwanted signals, the analog signal is processed

differentially until it is converted to digital data. The signal is amplified by the input amplifier at one of three

software-selectable gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the

input amplifier.

The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discrete digital

words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit

digital words, representing sampled values of the analog input signal, are clocked out of the serial port

(DOUT), one word for each primary communication interval. During secondary communications, the data

previously programmed into the registers can be read out with the appropriate register address and with the

read bit set to 1. When a register read is not requested, all 16 bits are 0.

2.5

DAC Signal Channel

DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications

interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog

voltage by the DAC with a sample and hold and then through a (sin x)/x correction circuit and a smoothing

filter. An output buffer with three software-programmable gains (0 dB, – 6 dB, and – 12 dB), as shown in

the output buffer. During secondary communications, the configuration program data are read into the

device control registers.

2.6

Serial Interface

The digital serial interface consists of the shift clock, the frame-synchronization signal, the ADC-channel

data output, and the DAC-channel data input. During the primary 16-bit frame-synchronization interval, the

SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.

During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT

when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into

DIN. The functional sequence is shown in Figure 2–1.

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