TLC320AC02 datasheet(15/84 Pages) TI

15 / 84 page

1–8

1.5

There are nine data registers that are used as follows:

The No-op register. The 0 address allows phase adjustments to be made without

reprogramming a data register.

The A register controls the count of the A counter.

The B register controls the count of the B counter.

The A

′ register controls the phase adjustment of the sampling period. The adjustment is

equal to the register value multiplied by the input master period.

The amplifier gain register controls the gains of the input, output, and monitor amplifiers.

The analog configuration register controls:

•

The addition/deletion of the high-pass filter to the ADC signal path

•

The enable/disable of the analog loopback

•

The selection of the regular inputs or auxiliary inputs

•

The function that allows processing of signals that are the sum of the regular inputs and

the auxiliary inputs (VIN + VAUX IN)

The digital configuration register controls:

•

Selection of the free-run function

•

FSD [frame-synchronization (sync) delay] output enable/disable

•

Selection of 16-bit function

•

Forcing secondary communications

•

Software reset

•

Software power down

The frame-sync delay register controls the time delay between the master-device frame

sync and slave-device frame sync. Register 7 must be the last register programmed when

using slave devices since all register data is latched and valid on the sixteenth falling edge

of SCLK. On the sixteenth falling edge of SCLK, all delayed frame-sync intervals are shifted

by this programmed amount.

The frame-sync number register informs the master device of the number of slaves that are

connected in the chain. The frame-sync number is equal to the number of slaves plus one.

TLC320AC02 Datasheet(PDF) 15 Page - Texas Instruments