TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

16

POST OFFICE BOX 655303

PRINCIPLE OF OPERATION

digital inputs (continued)

The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be

minimized by proper termination of the signal close to the TLV5535. An important cause of performance

degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the

ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by

formula shows the relation:

dtmax + 1 B p f2

N

)1

As an example, for an 8-bit converter with a 15-MHz input, the jitter needs to be kept < 41 pF in order not to have

changes in the LSB of the ADC output due to the total aperture error.

digital outputs

The output of the TLV5535 is standard binary code. Capacitive loading on the output should be kept as low as

possible (a maximum loading of 10 pF is recommended) to provide the best performance. Higher output loading

causes higher dynamic output currents and can increase noise coupling into the analog front end of the device.

To drive higher loads, the use of an output buffer is recommended.

When clocking output data from the TLV5535, it is important to observe its timing relation to CLK. The pipeline

ADC delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the

specification section for more details.

layout, decoupling and grounding rules

It is necessary for any PCB using the TLV5535 to have proper grounding and layout to achieve the stated

performance. Separate analog and digital ground planes that are spliced underneath the device are advisable.

The TLV5535 has digital and analog terminals on opposite sides of the package to make proper grounding

easier. Since there is no internal connection between the analog and digital grounds, they have to be joined on

the PCB. Joining the digital and analog grounds at a point in close proximity to the TLV5535 is advised.

the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output

buffers.

Due to the high sampling rate and switched-capacitor architecture, the TLV5535 generates transients on the

supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic

of the TLV5535 EVM is recommended.