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TLV5535IPW Datasheet(PDF) 17 Page - Texas Instruments |
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TLV5535IPW Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 32 page ![]() TLV5535 8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER SLAS221 – JUNE 1999 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5535 EVALUATION MODULE TLV5535 evaluation module TI provides an evaluation module (EVM) for TLV5535. The EVM also includes a 10b 80 MSPS DAC so that the user can convert the digitized signal back to the analog domain for functional testing. Performance measurements can be done by capturing the ADC’s output data. The EVM provides the following additional features: D Provision of footprint for the connection of an onboard crystal oscillator, instead of using an external clock input. D Use of TLV5535 internal or external voltage references. In the case of external references, an onboard circuit is used that derives adjustable bottom and top reference voltages from a bandgap reference. Two potentiometers allow for the independent adjustments of both references. The full scale ADC range can be adjusted to the input signal amplitude. D All digital output, control signal I/O (output enable, standby, reference powerdown) and clock I/O are provided on a single connector. The EVM can thus be part of a larger (DSP) system for prototyping. D Onboard prototyping area with analog and digital supply and ground connections. Figure 15 shows the EVM schematic. The EVM is factory shipped for use in the following configuration: D Use of external (onboard) voltage references D External clock input analog input A signal in the range between V(REFBI) and V(REFTI) should be applied to avoid overflow/underflow on connector J10. This signal is onboard terminated with 50 Ω. There is no onboard biasing of the signal. When using external (onboard) references, these levels can be adjusted with R7 (V(REFTI)) and R6 (V(REFBI)). Adjusting R7 causes both references to shift. R6 only impacts the bottom reference. The range of these signals for which the device is specified depends on AVDD and is shown in the Recommended Operating Conditions. Internally generated reference levels are also dependent on AVDD as shown in the electrical characteristics section. clock input A clock signal should be applied with amplitudes ranging from 0 to AVDD with a frequency equal to the desired sampling frequency on connector J9. This signal is onboard terminated with 50 Ω. Both ADC and DAC run off the same clock signal. Alternatively the clock can be applied from terminal 1 on connector J11. A third option is using a crystal oscillator. The EVM board provides the footprint for a crystal oscillator that can be populated by the end-user, depending on the desired frequency. The footprint is compatible with the Epson EG-8002DC series of programmable high-frequency crystal oscillators. Refer to the TLV5535 EVM Settings for selecting between the different clock modes. |
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