TLV5613 datasheet(13/21 Pages) TI

13 / 21 page

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER

WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

layout considerations

To achieve the best performance, it is recommended to have separate power planes for GND, AVDD, and DVDD.

Figure 15 shows how to lay out the power planes for the TLV5613. As a general rule, digital and analog signals

should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in

parallel. The two positive power planes ( AVDD and DVDD) should be connected together at one point with a

ferrite bead.

A 100-nF ceramic low series inductance capacitor between DVDD and GND and a 1-µF tantalum capacitor

between AVDD and GND as close as possible to the supply pins are recommended for optimal performance.

DVDD

AVDD

Figure 15. TLV5613 Board Layout

linearity, offset, and gain error using single end supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage

may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage remains at zero until the input code value produces a sufficient positive output voltage to

overcome the negative offset voltage, resulting in the transfer function shown in Figure 16.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 16. Effect of Negative Offset (Single Supply)

TLV5613 Datasheet(PDF) 13 Page - Texas Instruments