TLV986

3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR

SLAS228 – JULY 1999

18

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

CCD

1

CCD

2

CCD

3

CCD

4

CCD

1

CCD

2

CCD

3

CCD

4

SR

SV

CCD

Output

CDS OUT

(Internal)

OBCLP

ADCCLK

ADD255

(Internal)

OBPC

(Internal)

OBLC

(Internal)

ADC OUT

For Black Pixels

ADC

1

ADC

2

ADC

3

ADC

4

Initiates Internal Counters, etc.

2^N + 1 PIXELS

First Line

Second Line

PGA Samples

CCD1

During this interval an offset of 255 LSB is

intentionally added to the PGA output (see Note)

3 Half Cycles

Allow Settling

DACs Are Updated

2^N + 1 PIXELS

NOTE: To avoid the ADC being clipped on differential negative input signals, an internal offset that equals to 255 ADC LSBs is intentionally added

to the PGA output signal. This offset is only added during optical black pixel interval with a total duration of 2N + 3 pixels, where three

additional pixels are necessary for accommodating internal latency adjustment.

Figure 5. Optical Black and Offset Correction Timing