TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

40

POST OFFICE BOX 1443

timing of peripheral pin changing from general-purpose input to output mode (see Figure 34)

NO

’C32 - 40

’C32 - 50

’C32 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

98

td(GPIOH1H)

Delay time, H1 high to peripheral pin switching from input

to output

13

10

8

ns

Peripheral Pin

(see Note A)

I / O Control Bit

H1

H3

Execution of Store of

Peripheral Control

Register

98

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents

of internal control registers associated with each peripheral.

Figure 34. Timing of Peripheral Pin Changing From General-Purpose Input to Output Mode