TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

39

POST OFFICE BOX 1443

CREQx

CACKx

CSTRBx

CxDx

CRDYx

= When signal is an input (clear = when signal is an output).

Valid Data

1

5

6

7

8

3

4

2

Valid Data

NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7 – CxD0 are asserted by the ’C4x sending data. CREQx and CRDYx are

input signals asserted by the ’C4x receiving data and are asynchronous with respect to the H1 clock of the sending ’C4x. After token

exchange, CREQx and CRDYx become outputs, and CSTRBx, CACKx, and CxDx become inputs.