TMS320C40 datasheet(12/45 Pages) TI

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TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

description

The ’320C40 digital signal processors ( DSPs) are 32-bit, floating-point processors manufactured in 0.72-

µm,

double-level metal CMOS technology. The ’320C40 is a part of the fourth generation of DSPs from Texas

Instruments and is designed primarily for parallel processing.

operation

The ’320C40 has six on-chip communication ports for processor-to-processor communication with no external

hardware and simple communication software. This allows connectivity to other ’C4x processors with no

external-glue logic. The communication ports remove input / output bottlenecks, and the independent smart

DMA coprocessor is able to handle the CPU input / output burden.

central processing unit

The ’320C40 CPU is configured for high-speed internal parallelism for the highest sustained performance. The

key features of the CPU are:

D Eight operations/cycle:

–

40/32-bit floating-point / integer multiply

–

40/32-bit floating-point / integer ALU operation

–

Two data accesses

–

Two address register updates

D IEEE floating-point conversion

D Divide and square-root support

D ’C3x assembly language compatibility

D Byte and halfword accessibility

DMA coprocessor

The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance.

The key features of the DMA processor are:

D Link pointers allow DMA channels to auto-initialize without CPU intervention.

D Parallel CPU operation and DMA transfers

D Six DMA channels support memory-to-memory data transfers.

D Split-mode operation doubles the available DMA channel to 12 when data transfers to and from a

communication port are required.

communication ports

The ’320C40 is the first DSP with on-chip communication ports for processor-to-processor communication with

no external hardware and simple communication software. The features of the communication ports are:

D Direct interprocessor communication and processor I/O

D Six communication ports for direct interprocessor communication and processor I/O

D 20M-bytes/s bidirectional interface on each communication port for high-speed multiprocessor interface

D Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I/O

D Automatic arbitration and handshaking for direct processor-to-processor connection

TMS320C40 Datasheet(PDF) 12 Page - Texas Instruments

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