TMS320C40 datasheet(35/45 Pages) TI

35 / 45 page

TMS320C40

DIGITAL SIGNAL PROCESSOR

SPRS038 – JANUARY 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

communication-port byte-cycle timing (write and read) (see Note 11 and Figure 23)

NO.

TMS320C40 - 40

TMS320C40 - 50

TMS320C40 - 60

UNIT

MIN

MAX

MIN

MAX

tsu(CD-CSL)W

Setup time, CxDx valid before CSTRBx low (write)

td(CRDYL - CSH)W

Delay time, CRDYx low to CSTRBx high (write)

0†

th(CRDYL - CD)W

Hold time, CxDx after CRDYx low (write)

td(CRDYH - CSL)W

Delay time, CRDYx high to CSTRBx low for subsequent bytes

(write)

0†

tc(BYTE)‡

Cycle time, byte transfer

44§

td(CSL - CRDYL)R

Delay time, CSTRBx low to CRDYx low (read)

0†

tsu(CSH - CD)R

Setup time, CxDx valid after CSTRBx high (read)

th(CRDYL - CD)R

Hold time, CxDx valid after CRDYx low (read)

td(CSH - CRDYH)R

Delay time, CSTRBx high to CRDYx high (read)

0†

† This value is specified by design but not tested.

‡ tc(BYTE) max = summed maximum values of td(CRDY-CSH), td(CSL-CRDYL)R, td(CSH-CRDYH)R, and td(CRDYH-CSL)W. This assumes

two ’C4xs are connected.

§ This value is characterized but not tested.

NOTE 11: Communication port timing does not include line length delay.

CREQx

CACKx

CSTRBx

CxDx

CRDYx

(a) WRITE TIMING

(b) READ TIMING

Valid

Data

= When signal is an input (clear = when signal is an output).

Figure 23. Communication-Port Byte-Cycle Timing (Write and Read)

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