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TMS320C40 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C40 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 45 page  ‡ See Pin Assignments table and Pin Functions table for location and description of all pins. 1 2 3 4 5 6 7 8 9 10 11 13 12 15 14 16 17 18 19 20 21 22 23 24 25 26 28 27 30 29 31 32 33 34 35 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR Pin A1 325-PIN GF GRID ARRAY PACKAGE (BOTTOM VIEW)‡ x TMS320C40 DIGITAL SIGNAL PROCESSOR SPRS038 – JANUARY 1996 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D Highest Performance Floating-Point Digital Signal Processor (DSP) – ’320C40-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 384M Bytes / s – ’320C40-50: 40-ns Instruction Cycle Time – ’320C40-40: 50-ns Instruction Cycle Time D Six Communications Ports D Six-Channel Direct Memory Access (DMA) Coprocessor D Single-Cycle Conversion to and From IEEE-754 Floating-Point Format D Single Cycle, 1/x, 1/ D Source-Code Compatible With TMS320C3x D Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers D Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers D IEEE 1149.1† (JTAG) Boundary Scan Compatible D Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers: – High Port-Data Rate of 120M Bytes/s (’C40-60) (Each Bus) – 16G-Byte Continuous Program/ Data / Peripheral Address Space – Memory-Access Request for Fast, Intelligent Bus Arbitration – Separate Address-Bus, Data-Bus, and Control-Enable Pins – Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware D 325-Pin Ceramic Grid Array (GF Suffix) D Fabricated Using 0.72-µm Enhanced Performance Implanted CMOS (EPIC ™) Technology by Texas Instruments (TI ™) D Software-Communication-Port Reset D NMI With Bus-Grant Feature D Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input / Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance D On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance – 512-Byte Instruction Cache – 8K Bytes of Single-Cycle Dual-Access Program or Data RAM – ROM-Based Boot Loader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories or One of the Communication Ports D IDLE2 Clock-Stop Power-Down Mode D 5-V Operation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated † IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture EPIC and TI are trademarks of Texas Instruments Incorporated. |
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