TMS320F243 datasheet(97/116 Pages) TI

97 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external memory interface

write timings (continued)

tdis(W-D)

td(COH–A)W

td(COH–RWL)

tsu(A)W

td(COL–WH)

STRB

ten(D)COL

td(COL–WL)

th(A)COHW

td(COH–CNTL)

td(COH–CNTH)

CLKOUT

A[0:15]

R/W

PS, DS, IS, BR

td(COH–CNTL)

td(COH–RWH)

td(COL–WL)

td(COL–WH)

th(D)W

tsu(D)W

ten(D)COL

td(COL–SH)

VIS_CLK

ENA_144

VIS_OE

th(D)W

td(COL–SL)

NOTE A: ENA_144 when active low along with BVIS bits (10,9 set to 01 or 11) in register WSGR - IO@FFFFh, VIS_CLK and VIS_OE will be visible

at pins 31 (’F243) and 126 (’F243) respectively. VIS_CLK and VIS_OE indicate internal memory write cycles (program/data). During

VIS_OE cycles, the external bus will be driven. VIS_CLK is essentially CLKOUT, to be used along with VIS_OE for trace capabilities.

tsu(D)W

td(COL–SL)

D[0:15]

td(COL–SH)

Figure 39. Address Visibility Mode

TMS320F243 Datasheet(PDF) 97 Page - Texas Instruments

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