TMS320F243 datasheet(16/116 Pages) TI

16 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F241 PG and FN Packages (Continued)

NAME

QFP

PLCC

TYPE†

RESET

STATE‡

DESCRIPTION

NO.

STATE‡

CLOCK SIGNALS (CONTINUED)

CLKOUT/IOPD0

I/O

Clock output. This pin outputs either the CPU clock (CLKOUT) or the

watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14)

of the System Status and Control Register (SSCR). This pin can be used as

a GPIO if not used as a clock output pin.

TEST SIGNALS

TCK

JTAG test clock with internal pullup

TDI

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected

TDO

JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) is shifted out of TDO on the falling edge of TCK.

TMS

JTAG test-mode select (TMS) with internal pullup. This serial control input is

clocked into the TAP controller on the rising edge of TCK.

TRST

JTAG test reset with internal pulldown. TRST, when driven high, gives the

scan system control of the operations of the device. If this signal is not

connected or driven low, the device operates in its functional mode, and the

test reset signals are ignored.

EMU0

I/O

Emulator I/O pin 0 with internal pullup. When TRST is driven high, this pin is

used as an interrupt to or from the emulator system and is defined as

input/output through the JTAG scan.

EMU1

I/O

Emulator I/O pin 1 with internal pullup. When TRST is driven high, this pin is

used as an interrupt to or from the emulator system and is defined as

input/output through JTAG scan.

SUPPLY SIGNALS

VDD

–

Digital logic supply voltage (5 V)

VDD

–

Digital logic supply voltage (5 V)

–

VDDO

–

Digital logic and buffer supply voltage (5 V)

VDDO

–

Digital logic and buffer supply voltage (5 V)

–

VSS

–

Digital logic ground reference

–

VSSO

–

Digital logic and buffer ground reference

–

NO CONNECT

–

No internal connection made to this pin

DNC

–

Do not connect. Reserved for test.

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

NOTE:

Bold, italicized pin names indicate pin function after reset.

TMS320F243 Datasheet(PDF) 16 Page - Texas Instruments

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