TMS320F243 datasheet(10/116 Pages) TI

10 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE†

RESET

STATE‡

DESCRIPTION

NO.

STATE‡

INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS (CONTINUED)

PMT

Enables parallel module test (PMT). Do not connect, reserved for test.

VCCP/WDDIS

Flash programming voltage pin and watchdog disable. This is the 5-V supply used

for flash programming. Flash cannot be programmed if this pin is held at 0 V. This

pin also works as a hardware watchdog disable, when VCCP/WDDIS = +5 V and

bit 6 in WDCR is set to 1.

DEDICATED I/O SIGNALS

IOPD2

I/O

Dedicated GPIO – Port D bit 2

IOPD3

I/O

Dedicated GPIO – Port D bit 3

IOPD4

I/O

Dedicated GPIO – Port D bit 4

IOPD5

I/O

Dedicated GPIO – Port D bit 5

IOPD6

I/O

Dedicated GPIO – Port D bit 6

IOPD7

I/O

Dedicated GPIO – Port D bit 7

DATA AND ADDRESS BUS SIGNALS

I/O/Z

O¶

Bit x of the 16 bit Data Bus

I/O/Z

O¶

Bit x of the 16-bit Data Bus

D10

D11

D12

D13

D14

D15

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶ Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS

is enabled.

NOTE:

Bold, italicized pin names indicate pin function after reset.

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