TMS320VC549 datasheet(8/60 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

’549 Signal Descriptions (Continued)

TERMINAL

DESCRIPTION

NAME

DESCRIPTION

TYPE†

MEMORY CONTROL SIGNALS (CONTINUED)

IAQ

O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address

bus and goes into the high-impedance state when EMU1/OFF is low.

OSCILLATOR/TIMER SIGNALS

CLKOUT

O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle

is bounded by the falling edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF

is low.

CLKMD1

CLKMD2

CLKMD3

Clock mode external/internal input signals. CLKMD1, CLKMD2, and CLKMD3 allow you to select and configure

different clock modes, such as crystal, external clock, and various PLL factors. Refer to PLL section for a detailed

functional description of these pins.

X2/CLKIN

Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can

become input to the device using this pin. The internal machine cycle time is determined by the clock

operating-mode pins (CLKMD1, CLKMD2 and CLKMD3).

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.

TOUT

O/Z

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT-cycle

wide. TOUT also goes into the high-impedance state when EMU1/OFF is low.

BUFFERED SERIAL PORT 0 AND BUFFERED SERIAL PORT 1 SIGNALS

BCLKR0

BCLKR1

Receive clocks. External clock signal for clocking data from the data-receive (DR) pin into the buffered serial port

receive shift registers (RSRs). Must be present during buffered serial port transfers. If the buffered serial port is

not being used, BCLKR0 and BCLKR1 can be sampled as an input by way of IN0 bit of the SPC register.

BCLKX0

BCLKX1

I/O/Z

Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit

(DX) pin. BCLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven

by the device at 1/(CLKDV + 1) where CLKDV range is 0–31 CLKOUT frequency when MCM is set to 1. If the

buffered serial port is not used, BCLKX can be sampled as an input by way of IN1 of the SPC register. BCLKX0

and BCLKX1 go into the high-impedance state when OFF is low.

BDR0

BDR1

Buffered serial-data-receive input. Serial data is received in the RSR by BDR0/BDR1.

BDX0

BDX1

O/Z

Buffered serial-port-transmit output. Serial data is transmitted from the XSR by way of BDX. BDX0 and BDX1 are

placed in the high-impedance state when not transmitting and when EMU1/OFF is low.

BFSR0

BFSR1

Frame synchronization pulse for receive input. The falling edge of the BFSR pulse initiates the data-receive

process, beginning the clocking of the RSR.

BFSX0

BFSX1

I/O/Z

Frame synchronization pulse for transmit input/output. The falling edge of the BFSX pulse initiates the

data-transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of

BFSX is an input. BFSX0 and BFSX1 can be selected by software to be an output when TXM in the serial control

SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS

CLKR0

CLKR1

Receive clocks. External clock signal for clocking data from the data receive (DR) pin into the serial port receive

shift register (RSR). Must be present during serial port transfers. If the serial port is not being used, CLKR0 and

CLKR1 can be sampled as an input via IN0 bit of the SPC register.

CLKX0

CLKX1

I/O/Z

Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit

(DX) pin. CLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven by

the device at 1/4 CLKOUT frequency when MCM is set to 1. If the serial port is not used, CLKX can be sampled

as an input via IN1 of the SPC register. CLKX0 and CLKX1 go into the high-impedance state when EMU1/OFF

is low.

DR0

DR1

Serial-data-receive input. Serial data is received in the RSR by DR.

† I = Input, O = Output, Z = High impedance

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