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TMS320VC549 Datasheet(PDF) 12 Page - Texas Instruments |
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TMS320VC549 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 60 page ![]() TMS320VC549 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended operating case temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage‡ VDD = 3.3"0.3 V, IOH = MAX 2.4 V VOL Low-level output voltage‡ IOL = MAX 0.4 V IIZ Input current in high A[22:0] VDD = MAXk –150 250 µA IIZ In ut current in high impedance All other pins VDD = MAX, VI = VSS to VDD –10 10 µA TRST With internal pulldown –10 800 HPIENA With internal pulldown, RS = 0 –10 400 I Input current TMS, TCK, TDI, HPI|| With internal pullups –400 10 A II In ut current (VI = VSS to VDD) D[15:0], HD[7:0] Bus holders enabled, VDD = MAXk –150 250 µA ( ISS DD) X2/CLKIN Oscillator enabled –40 40 All other input-only pins –10 10 IDDC Supply current, core CPU CVDD = 2.5 V, fx = 40 MHz,§ TC = 25°C 20¶ mA IDDP Supply current, pins DVDD = 3.3 V, fx = 40 MHz,§ TC = 25°C 12# mA IDLE2 PLL × 1 mode, 40 MHz input 2 mA IDD Supply current, standby IDLE3 Divide-by-two mode, CLKIN stopped (’VC549-80 and ’VC549-100) 15 µA DD standby IDLE3 Divide-by-two mode, CLKIN stopped (’VC549-120 only) 170 µA Ci Input capacitance 10 pF Co Output capacitance 10 pF † All values are typical unless otherwise specified. ‡ All input and output voltage levels except RS, INT0–INT3, NMI, CNT, X2/CLKIN, CLKMD0–CLKMD3 are LVTTL-compatible. § Clock mode: PLL × 1 with external source ¶ This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed. # This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed, refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164). || HPI input signals except for HPIENA. kVIL(MIN) ≤ VI ≤ VIL(MAX) or VIH(MIN) ≤ VI ≤ VIH(MAX) |
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