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TMS320VC549 Datasheet(PDF) 20 Page - Texas Instruments |
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TMS320VC549 Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 60 page  TMS320VC549 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory and parallel I/O interface timing (continued) timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 5) ’549-80 ’549-100 ’549-120 UNIT MIN MAX MIN MAX MIN MAX UNIT ta(A)M Access time, read data access from address valid 2H–9 2H–8 2H–8 ns ta(MSTRBL) Access time, read data access from MSTRB low 2H–8 2H–7 2H–7 ns tsu(D)R Setup time, read data before CLKOUT low 5 5 5 ns th(D)R Hold time, read data after CLKOUT low 0 0 0 ns th(A-D)R Hold time, read data after address invalid 0 0 0 ns th(D)MSTRBH Hold time, read data after MSTRB high 0 0 0 ns † Address, PS, and DS timings are all included in timings referenced as address. ‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance. |
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