TMS3637P datasheet(46/53 Pages) TI

46 / 53 page

6–14

Table 6–7. TRF1400 RF Receiver and TCM3637 Decoder Parts List

(for 300 MHz operation) (continued)

DESIGNATORS

DESCRIPTION

VALUE

MANUFACTURER

MANUFACTURER P/N

Inductor

47 nH

Coilcraft

0805HS470TMBC

Inductor

82 nH

Coilcraft

0805HS820TKBC

Inductor

120 nH

Coilcraft

0805HS121TKBC

Inductor

39 nH

Coilcraft

0805HS390TMBC

RF SMA Connector

Johnson

142–0701–201

Resistor

1200

Ω

Resistor

1200

Ω

Resistor

Ω

Resistor

130 K

Ω, 1%

Resistor

Ω

Resistor

1 K

Ω

Resistor

100

Ω

Resistor

1 K

Ω

Resistor

27 k

Ω

R10

Resistor

Ω

RF Receiver

Texas Instruments

TRF1400

Decoder

Texas Instruments

TMS3637

6.7

Programming Station

A programming station schematic is shown in Figure 6–9. This station is made up of two major parts: 1)a

shift register/clock circuit that outputs exactly 35 bits serially (four reset pulses, 22 security bits, and 9

configuration bits), and 2) a transistor ramp generator that outputs the programming pulse required to store

data in the EEPROM. The following paragraphs detail the function of the circuit.

Before the momentary switch SW5 is pressed, the shift registers U9–U13 shift-load input is low so that they

are continually loading whatever code is present on the DIP switches SW1–SW4. In addition, the binary

counter U6 is in a clear state and its output is 00000000.

When momentary switch SW5 is pressed, the set-reset (S-R) latch on U1 acts as a debouncer and outputs

a logic level 1, which releases the clear on binary counter U6. It places a high on the shift input to the shift

registers

U9 – U13, allowing them to shift out the stored 35 bits as soon as a clock is applied to them. The output of

the S-R latch on U1 is also connected to the D input of the D flip-flop on U2. The D flip-flop is clocked by

the free-running 555 timer (U8) configured for astable operation on a 8-kHz clock. Therefore, on the next

rising edge of the U8 clock, the D flip-flop on U2 outputs a high signal. The output of the D flip-flop enables

the AND gate on U3 to pass the 8-kHz clock. The 8-kHz clock signal is routed to the dual 4-bit binary counters

(U6) that have had their CLR terminal released by the S-R latch (from pressing the momentary switch SW5).

The outputs of the U6 counters are connected to the counter-comparator U7, which outputs low when the

count reaches exactly 35 clock pulses (as defined by the code 11000100 on U7 Q inputs). The output of U7

then clears the D flip-flop on U2, the 8-kHz clock is no longer able to pass, and the counting stops.

During this entire counting sequence, the shift registers U9 through U13 are clocked with exactly 35 bits.

Due to the momentary switch being pressed, the S-R latch output is high on the shift-register shift enable,

allowing the registers to shift out the 35 bits of data to the code input of the TMS3637. The TMS3637 is

clocked synchronously with this data on OSCR.

Because the binary counter U6 is released from its cleared state and the U9–U13 registers are allowed to

shift data only during the time that the momentary switch is pressed, it is required that the switch be held

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