TP3064B, TP3067B, TP13064B, TP13067B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

7

POST OFFICE BOX 655303

timing requirements

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

fclock(M) Frequency of master clock

MCLX

and

MCLKR

Depends on the device used and

BCLKX/CLKSEL

1.536

1.544

2.048

MHz

fclock(B)

Frequency of bit clock, transmit

BCLKX

64

2.048

MHz

tr1

Rise time of master clock

MCLKX

and

MCLKR

Measured from 20% to 80%

50

ns

tf1

Fall time of master clock

MCLKX

and

MCLKR

Measured from 20% to 80%

50

ns

tr2

Rise time of bit clock, transmit

BCLKX

Measured from 20% to 80%

50

ns

tf2

Fall time of bit clock, transmit

BCLKX

Measured from 20% to 80%

50

ns

tw1

Pulse duration, MCLKX and MCLKR high

160

ns

tw2

Pulse duration, MCLKX and MCLKR low

160

ns

tsu1

Setup time, BCLKX high (and FSX in long-frame

sync mode) before MCLKX

↓

First bit clock after the leading edge

of FSX

100

ns

tw3

Pulse duration, BCLKX and BCLKR high

VIH = 2.2 V

160

ns

tw4

Pulse duration, BCLKX and BCLKR low

VIL = 0.6 V

160

ns

th1

Hold time, frame sync low after bit clock low (long

frame only)

0

ns

th2

Hold time, BCLKX high after frame sync

↑ (short

frame only)

0

ns

tsu2

Setup time, frame sync high before bit clock

↓ (long

frame only)

80

ns

td1

Delay time, BCLKX high to data valid

Load = 150 pF plus 2 LSTTL loads‡

0

140

ns

td2

Delay time, BCLKX high to TSX low

Load = 150 pF plus 2 LSTTL loads‡

140

ns

td3

Delay time, BCLKX (or 8 clock FSX in long frame

only) low to data output disabled

50

165

ns

td4

Delay time, FSX or BCLKX high to data valid (long

frame only)

CL = 0 pF to 150 pF

20

165

ns

tsu3

Setup time, DR valid before BCLKR

↓

50

ns

th3

Hold time, DR valid after BCLKR or BCLKX

↓

50

ns

tsu4

Setup time, FSR or FSX high before BCLKR or

BCLKX

↓

Short-frame sync pulse (1- or 2-bit

clock periods long) (see Note 3)

50

ns

th4

Hold time, FSX or FSR high after BCLKX or

BCLKR

↓

Short-frame sync pulse (1- or 2-bit

clock periods long) (see Note 3)

100

ns

th5

Hold time, frame sync high after bit clock

↓

Long-frame sync pulse (from 3- to

8-bit clock periods long)

100

ns

tw5

Pulse duration of the frame sync pulse (low level)

64 kbps operating mode

160

ns

† All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

‡ Nominal input value for an LSTTL load is 18 k

Ω.

NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.