TP3064B, TP3067B, TP13064B, TP13067B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

17

POST OFFICE BOX 655303

PRINCIPALS OF OPERATION

transmit section

The transmit section input is an operational amplifier with provision for gain adjustment using two external

resistors. Gains in excess of 20 dB across the audio pass band are possible via low noise and wide bandwidth.

The operational amplifier drives a unity-gain filter consisting of an RC active prefilter followed by an eight-order

switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter directly drives the encoder

sample-and-hold circuit. As per

µ-law (TP3064B and TP13064B) or A-law (TP3067B and TP13067B) coding

conventions, the ADC is a companding type. A precision voltage reference provides a input overload of

nominally 2.5-V peak. The sampling of the filter output is controlled by the FSX frame-sync pulse. Then the

successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and shifted out through

DX at the next FSX pulse. The total encoding delay is approximately 290

µs. Any offset voltage due to the filters

or comparator is cancelled by sign bit integration (see Table 2).

Table 2. Encoding Format at DX Output

TP3064B, TP13064B

µ-LAW

TP3067B, TP13067B

A-LAW

(INCLUDES EVEN-BIT INVERSION)

VI = + Full scale

1 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0

VI = 0

1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1

1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1

VI = – Full scale

0 0 0 0 0 0 0 0

0 0 1 0 1 0 1 0

receive section

The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.

The decoder is

µ-law (TP3064B and TP13064B) or A-law (TP3067B and TP13067B) and the fifth-order

low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by

a second-order RC active post-filter with its output at VFRO. The receive section is unity-gain but gain can be

added by using the power amplifiers. At FSR, the data at DR is clocked in on the falling edge of the next eight

BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10

µs later the

decoder DAC output is updated. The decoder delay is about 10

µs (decoder update) plus 110 µs (filter delay)

plus 62.5

µs (1/2 frame), or a total of approximately180 µs.

receive power amplifiers

Two inverting-mode power amplifiers are provided for directly driving a match-line interface transformer. The

gain of the first power amplifier can be adjusted to boost the

±2.5-V peak output signal from the receive filter

up to the

±3.3-V peak into an unbalanced 300-Ω load, or ±4 V into an unbalanced 15-kΩ load. The second power

amplifier is internally connected in unity-gain inverting mode to give 6-dB signal gain for balanced loads.

Maximum power transfer to a 600-

Ω subscriber line termination is obtained by differentially driving a balanced

transformer with

√2:1 turns ratio, as shown in Figure 3. A total peak power of 15.6 dBm can be delivered to the

load plus termination.