LE25FW808

No.A0839-3/27

Figure 2 Block Diagram

Table 1 Pin Description

*( ) HD_READ mode

Symbol

Pin Name

Description

SCK

Serial clock

This pin controls the data input/output timing.

SI

(SIO0)

Serial data input

(Serial data I/O0)

To input data or addresses serially from MSB to LSB (Least Significant Bit).

(To input data or addresses and to output data serially in the HD_READ mode)

SO

(SIO3)

Serial data output

(Serial data I/O3)

To output data serially from MSB to LSB.

(To input data or addresses and to output data serially in the HD_READ mode)

CS

Chip select

The device becomes active when the logic level of this pin is low; it is deselected and placed in standby

status when the logic level of the pin is high.

WP

(SIO2)

Write-protect

(Serial data I/O2)

To write-protect the block protect bits (BP0, BP1, BP2) and the status register write protect bit (SRWP) of the

status register in co-operation with the status register write protect bit (SRWP).

(To input data or addresses and to output data serially in the HD_READ mode)

HOLD

(SIO1)

Hold

(Serial data I/O1)

To pause any serial communications with the device without deselecting the device.

(To input data or addresses and to output data serially in the HD_READ mode)

VDD

Power supply

This pin supplies the 2.7 to 3.6V supply voltage.

VSS

Ground

This pin supplies the 0V supply voltage.

8M Bit

Flash EEPROM

Cell Array

Y-DECODER

I/O BUFFERS

&

DATA LATCHES

CS

SCK

SI

(SIO0)

HOLD

(SIO1)

WP

(SIO2)

SO

(SIO3)

X-

DECODER

ADDRESS

BUFFERS

&

LATCHES

SERIAL INTERFACE

CONTROL

LOGIC