5

UCC1583

UCC2583

UCC3583

For the circuit shown in Figure 5a, CC1 is charged when

the transformer voltage is positive and the synchronous

switch is on. During the off period of Q-SYNC, the charge

is transferred to CC2 through diode DC2. Diode DC3

charges CC2 during the blocking interval of Q-SYNC.

This method is preferable when the transformer positive

voltage is high enough to generate the required bias volt-

age. For the circuit shown in Figure 5b, CC1 is charged

during the period when reverse (reset) voltage appears

across the secondary. The charge on CC1 is transferred

to CC2 through DC2 when Q-SYNC turns on. This

method is preferable when the reverse voltage is high

enough to generate the required bias voltage. The series

resistor should be chosen to handle the required voltage

drop at full IC operating current when the zener clamp

across VDD and COM is activated.

The following is a description of the major functional

blocks of the UCC3583. Refer to Figure 6 (Typical Appli-

cation Circuit) for component designations.

UVLO and Start Up

The UCC3583 has an internal undervoltage lockout cir-

cuit which keeps the internal circuitry inactive until VDD

exceeds the upper threshold (9V). Once the chip is acti-

vated, VDD has to be above the lower UVLO threshold

(8.4V) for it to remain functional. The IC requires a low

startup current of only 100

µA when VDD is under the

UVLO threshold. VDD has an internal clamp of 14V

which can sink up to 10mA. Measures must be taken not

to exceed this current. The internal reference (REF) is

brought up when the UVLO on threshold is exceeded.

The soft start pin provides an effective means to start the

IC in a controlled manner. An internal current of 10

µA

starts discharging a capacitor connected to SS when the

UVLO conditions have been removed. The voltage on

SS controls the duty cycle of the output during the dis-

charge period.

Synchronizing Circuit and Oscillator

UCC3583 is primarily intended for synchronizable opera-

tion where its switching frequency is determined by the

secondary pulse of the power transformer. However, it

has an internal oscillator which allows it to operate in

free-running mode when an external synchronization

pulse is not available. The switching frequency is deter-

The frequency is given by:

CH

DIS

CH

T

T

=

+

=•

•

and

()

()

DIS

T

RAMP p p

RAMP dis

T

=

•

ť

`

that the ramp is discharged through an internal imped-

ensure that the internal discharge current is the current

sired frequency of operation.

When the synchronizing signal is available, the oscillator

frequency should be programmed to be lower than the

synchronizing frequency to ensure proper operation. A

large difference in self-running and synchronizing fre-

quencies leads to smaller ramp amplitude and higher

noise sensitivity. The ramp capacitor is discharged when

the synchronization signal arrives and begins charging

when the low threshold is crossed.

There are two methods to synchronize to the secondary

pulse. One method is to use the rising edge of the sec-

ondary pulse, which reduces the maximum duty cycle

available. Subsequently, the post regulator switch cannot

method is to use the falling edge of the secondary pulse

for synchronization. This method is preferable because it

allows a slower discharge of the ramp capacitor without

affecting the maximum available duty cycle of the post

regulator. The UCC3583 SYNC input needs to reach a

fixed threshold (1.0V typical) for synchronization to take

effect. Hence the IC is usable with either method of syn-

chronization. However, the UCC3583 oscillator configu-

ration is better suited for synchronization to the falling

edge. A recommended method to implement the syn-

chronization is shown in Figure 6. By connecting SYNC

to a resistive divider between REF and the secondary

terminal S2, the synchronization is achieved whenever

SYNC pin varies from 0V to 1V. Placement of a Schottky

diode from SYNC to COM prevents the voltage at SYNC

from going negative. The internal hysteretic SYNC com-

parator has an inverting input set to 0.5V with about

±0.5V hysteresis.

PWM Comparator

The UCC3583 uses a leading edge PWM scheme. In a

leading edge PWM, the output pulse (gate signal) is

turned on when the error amplifier crosses the PWM

ramp and turned off by the clock/oscillator. Leading edge

modulation is naturally provided by magamp type post

regulators and is an essential feature for post regulators.

Without the leading edge modulation in a multiple output

APPLICATION INFORMATION (cont.)