6

UCC1583

UCC2583

UCC3583

converter with post regulation on one or more outputs,

the primary current shape does not remain monotonic

and can lead to instability when the primary current is

used for current mode control or current limiting. When

compared to conventional trailing edge PWMs, the lead-

ing edge modulation leads to a phase inversion that

needs to be accounted for in the feedback loop. For the

UCC3583, this inversion is automatically provided since

the sensed voltage at the power supply output negative

terminal has a negative polarity with respect to the chip

common. Thus, UCC3583 does not require inverting

buffers which would otherwise be needed.

Error Signal Generation and Current Limiting

The PWM comparator in the UCC3583 is controlled by

three parallel loops with only one of them in effect at a

time. During normal operation, the voltage error amplifier

output is fed to the PWM comparator. The voltage error

amplifier can be compensated using commonly used

feedback techniques to achieve the desired dynamic per-

formance. The ouput drive capability of the voltage am-

plifier

is

limited

to

100

µA, so appropriately high

impedances should be used to utilize the full output

swing of the amplifier. During startup, the soft start ca-

pacitor controls the pulse width. The third control loop is

provided by the average current amplifier. By sensing the

instantaneous inductor current and filtering/averaging it

with the current error amplifier, accurate current limiting

is achieved. This loop is in effect only during the overcur-

rent mode and provides a more accurate and noise free

control of the maximum output current compared to con-

ventional peak current limiting circuits. The current limit is

set by programming the voltage at ILIM based on the

current sense resistor chosen. In addition, the current

limit can be made proportional to the output voltage in or-

der to limit the power dissipation under short circuit con-

ditions. This is implemented by inserting a bias voltage

on CS which is proportional to the output voltage.

Gate Drive Circuit

The gate drive circuit of the UCC3583 provides high cur-

rent drive capability and is very easy to implement as a

result of tying the chip common to the source of the

switching device. Turn on current is higher (1.5A) as fast

turn on is essential for low losses and effective operation.

During the turn off, the drain voltage disappears, so turn

off time can be slower without increasing switching

losses.

APPLICATION INFORMATION (cont.)

Figure 1. UCC3583 SSPR system application and typical waveforms.

UDG-98195