5

UCC1921

UCC2921

UCC3921

Figure 2. Retry Operation Mode

UDG-96276

t0: Safe condition. Output current is nominal, output

voltage is at the negative rail, VSS.

t1: Fault control reached. Output current rises above

the programmed fault value, CT begins to charge at

~36

µA.

t2: Maximum current reached. Output current reaches

the programmed maximum level and becomes a con-

t3: Fault occurs. CT has charged to 2.5V, fault output

goes high, the FET turns off allowing no output current

t4: Retry. CT has discharged to 0.5V, but fault current is

still exceeded, CT begins charging again, FET is on,

t5 = t3: Illustrates 3% duty cycle.

t6 = t4: Retry. CT has discharged to 0.5V, but fault is

still exceeded, CT begins charging again, FET is on,

ground, CT charges at a higher rate depending upon

t8: Fault occurs. Output is still short circuited, but the

occurrence of a fault turns the FET off so no current is

conducted.

t9 = t4: Output short circuit released, still in fault mode.

t10 = t0: Fault released, safe condition. Return to nor-

mal operation of the hot swap power manager.

APPLICATION INFORMATION (continued)

Figure 1 shows the detailed circuitry for the fault timing

function of the UCC3921. For the time being, we will dis-

cuss a typical fault mode, therefore, the overload com-

parator, and current source I3 does not work into the

operation. Once the voltage across the current sense re-

causes the timing capacitor to charge with a combination

of 36

µA plus the current from the power limiting amplifier.

The PL amplifier is designed to only source current into

the CT pin and to begin sourcing current once the volt-

is related to the voltage across the FET with the following

expression:

I

VV

R

PL

FET

PL

=

− 5

Later it will be shown how this feature will limit average

power dissipation in the pass device. Note that under a

condition where the output current is more than the fault