6

UCC1921

UCC2921

UCC3921

Figure 3. Latched Operation Mode: R

APPLICATION INFORMATION (cont.)

UDG-96277

t0: Safe condition. Output current is nominal, output

voltage is at the negative rail, VSS.

t1: Fault control reached. Output current rises above

the programmed fault value, CT begins to charge at

~36

µA.

t2: Maximum current reached. Output current reaches

the programmed maximum level and becomes a con-

t3: Fault occurs. CT has charged to 2.5V, fault output

goes high as indicated by the SDFLTCH voltage. The

floats up to ground, and since there is an 82k

Ω resistor

from the SDFLTCH pin to VSS, the internal latchset sig-

nal goes high.

t4: Since the user does not want the chip to LATCH off

during this cycle, he toggles SDFLTCH high for greater

than 1ms {t6 - t4 > 1ms}.

t5: The latchset signal is reset.

t6: Forcing of SDFLTCH is released after having been

applied for > 1ms.

t7: Retry (since the latchset signal has been reset to its’

low state) - CT has discharged to 0.5V, but fault current

is still exceeded, CT begins charging again, FET is on,

t8 = t3: Fault occurs. CT has charged to 2.5V, fault out-

put goes high as indicated by the SDFLTCH voltage,

the FET turns off allowing no output current to flow,

resistor from SDFLTCH to VSS, the internal latchset

signal goes high.

t9: Output is latched off. Even though CT has dis-

charged to 0.5V, there will not be a retry since the

latchset signal was allowed to remain high.

t10: Output remains latched off. CT has discharged all

the wayto0V.

t11: The output has been latched off for quite some

time. The user now wishes to reset the latched off out-

put, thus toggling SDFLTCH high for greater than 1ms

{t13 - t11}.

t12 = t5: The latchset signal is reset.

t13: Forcing of SDFLTCH is released after having been

applied for > 1ms. The fault had also been released

during the time the output was latched off, safe condi-

tion, return to normal operation of the hot swap power

manager.