LTM9002 datasheet(12/28 Pages) LINER

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LTM9002

9002f

Control Pins

ADCSHDNA (Pin G7): Channel A Shutdown Mode Selec-

tion Pin. Connecting ADCSHDNA to GND and OEA to GND

results in normal operation with the outputs enabled.

Connecting ADCSHDNA to GND and OEA to VDD results

in normal operation with the outputs at high impedance.

Connecting ADCSHDNA to VDD and OEA to GND results in

nap mode with the outputs at high impedance. Connecting

ADCSHDNA to VDD and OEA to VDD results in sleep mode

with the outputs at high impedance.

ADCSHDNB (Pin C7): Channel B Shutdown Mode Selec-

tion Pin. Connecting ADCSHDNB to GND and OEB to GND

results in normal operation with the outputs enabled.

Connecting ADCSHDNB to GND and OEB to VDD results

in normal operation with the outputs at high impedance.

Connecting ADCSHDNB to VDD and OEB to GND results in

nap mode with the outputs at high impedance. Connecting

ADCSHDNB to VDD and OEB to VDD results in sleep mode

with the outputs at high impedance.

AMPSHDNA (Pin E1): Power Shutdown Pin for Channel A

Ampliﬁer. This pin is a logic input referenced to analog

ground. AMPSHDN = low results in normal operation.

AMPSHDN = high results in powered down ampliﬁer with

a <1mA ampliﬁer supply current.

AMPSHDNB (Pin E2): Power Shutdown Pin for Channel B

Ampliﬁer. This pin is a logic input referenced to analog

ground. AMPSHDN = low results in normal operation.

AMPSHDN = high results in powered down ampliﬁer with

a <1mA ampliﬁer supply current.

MODE (Pin G8): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Note that MODE controls both

channels. Connecting MODE to GND selects straight binary

output format and turns the clock duty cycle stabilizer off.

1/3 VDD selects straight binary output format and turns

the clock duty cycle stabilizer on. 2/3 VDD selects 2’s

complement output format and turns the clock duty cycle

stabilizer on. VDD selects 2’s complement output format

and turns the clock duty cycle stabilizer off.

MUX (Pin C8): Digital Output Multiplexer Control. If MUX

= high, channel A comes out on DAx; channel B comes

out on DBx. If MUX = low, the output busses are swapped

and channel A comes out on DBx; channel B comes out

on DAx. To multiplex both channels onto a single output

bus, connect MUX, CLKA and CLKB together.

OEA (Pin F8): Channel A Output Enable Pin. Refer to

ADCSHDNA pin function.

OEB (Pin D8): Channel B Output Enable Pin. Refer to

ADCSHDNB pin function.

SENSEA (Pin J4): Channel A Reference Programming Pin.

Connecting SENSEA to VDD selects the internal reference

and the higher input range. Connecting to 1.5V selects the

lower range. An external reference greater than 0.5V and

less than 1V applied to SENSEA selects an input range of

±VSENSEA/GAIN. See SENSE Pin Operation section.

SENSEB (Pin J3): Channel B Reference Programming Pin.

Connecting SENSEB to VDD selects the internal reference

and the higher input range. Connecting to 1.5V selects the

lower range. An external reference greater than 0.5V and

less than 1V applied to SENSEB selects an input range of

±VSENSEB/GAIN. See SENSE Pin Operation section.

Digital Inputs (Not Connected on LTM9002-LA)

CS/LD (Pin F3): Serial Interface Chip Select/Load Input

for Auxiliary DAC. When CS/LD is low, SCK is enabled

for shifting data on SDI into the register. When CS/LD is

taken high, SCK is disabled and the speciﬁed command

(see Table 3) is executed.

SCK (Pin F4): Serial Interface Clock Input for Auxiliary

DAC. CMOS and TTL compatible.

SDI (Pin D4): Serial Interface Data Input for Auxiliary

DAC. Data is applied to SDI for transfer to the device at

the rising edge of SCK. The auxiliary DAC accepts input

word lengths of either 24 or 32 bits.

PIN FUNCTIONS

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