LTM9002 datasheet(17/28 Pages) LINER

17 / 28 page

LTM9002

9002f

OPERATION

Note that not all combinations in Table 1 are possible at

this time and speciﬁed performance may differ signiﬁcantly

from existing values.

AMPLIFIER OPERATION

The ampliﬁers used in the LTM9002 are low noise and

low distortion fully differential op amps/ADC drivers with

operation from DC to 2GHz (–3dB bandwidth). The ampli-

ﬁers are composed of fully differential ampliﬁers with on

chip feedback and output common mode voltage control

circuitry. Differential gain and input impedance are set by

internal resistors in the feedback network.

Table 2. Ampliﬁer Gain and Input Impedance

GAIN (dB)

GAIN (V/V)

ZIN (DIFFERENTIAL)

2.5

400Ω

200Ω

50Ω

The ampliﬁers are very ﬂexible in terms of I/O coupling.

They can be AC- or DC-coupled at the inputs. Due to the

internal connection between input and output, users are

advised to keep input common mode voltage between 1V

and 1.7V for proper operation. If the inputs are AC-coupled,

the input common mode voltage is automatically biased

close to the ADC input common mode voltage and thus no

external circuitry is needed for bias. The input signal can

be either single-ended or differential with some difference

in distortion performance.

ADC INPUT NETWORK

The passive network between the ampliﬁer output stage

and the ADC input stage provides a 3rd order topology

that can be conﬁgured for bandpass or lowpass response

and different cutoff frequencies and bandwidths. LTM9002-

AA, for example, implements a lowpass ﬁlter designed

for 170MHz.

CONVERTER OPERATION

As shown in the Block Diagram, the analog-to-digital con-

verter (ADC) is a dual CMOS pipelined multistep converter.

The converter has six pipelined ADC stages; a sampled

analog input will result in a digitized value six cycles

later (see the Timing Diagram section). The CLK inputs

are single-ended. The ADC has two phases of operation,

determined by the state of the CLK input pins.

Each pipelined stage shown in the Block Diagram contains

an ADC, a reconstruction DAC and an interstage residue

ampliﬁer. In operation, the ADC quantizes the input to

the stage and the quantized value is subtracted from the

input by the DAC to produce a residue. The residue is

ampliﬁed and output by the residue ampliﬁer. Successive

stages operate out of phase so that when the odd stages

are outputting their residue, the even stages are acquiring

that residue and visa versa.

When CLK is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the Block Diagram. At the instant

that CLK transitions from low to high, the sampled input is

held. While CLK is high, the held input voltage is buffered

by the S/H ampliﬁer which drives the ﬁrst pipelined ADC

stage. The ﬁrst stage acquires the output of the S/H dur-

ing this high phase of CLK. When CLK goes back low, the

ﬁrst stage produces its residue which is acquired by the

second stage. At the same time, the input S/H goes back to

acquiring the analog input. When CLK goes back high, the

second stage produces its residue which is acquired by the

third stage. An identical process is repeated for the third,

fourth and ﬁfth stages, resulting in a ﬁfth stage residue

that is sent to the sixth stage ADC for ﬁnal evaluation.

Each ADC stage following the ﬁrst has additional range to

accommodate ﬂash and ampliﬁer offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

AUXILIARY DAC OPERATION

The full-scale voltage span of each ADC is controlled by an

auxiliary voltage output DAC connected to SENSE. Series

resistance in the DAC output allows an external voltage

to override the DAC.

The internal reference sets both auxiliary DACs to a full-

scale range to 1.5V. Programming the DAC to generate

an internal voltage greater than or less than the external

LTM9002 Datasheet(PDF) 17 Page - Linear Technology

LTM9002 Datasheet(HTML) 17 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL