SH7136/SH7137 Group

SCI Clock Synchronous Simultaneous Transmit and

Receive of Serial Data and DTC Data Transfer

REJ06B0890-0100/Rev.1.00

July 2009

Page 7 of 22

(1) Allocation of Transfer Information

Figure 4 shows the allocation of DTC transfer information in normal mode. The DTC transfer information is assigned

to a data area in a location such as on-chip RAM. Use address 4n as the start address for transfer information. If an

address other than 4n is specified, the lowest two bits are ignored when access is performed (lowest 2 bits = B'00).

Allocation of transfer

information in normal mode

Start address

Lower addresses

Transfer information

for one transfer round

(4 longwords)

01

23

MRB

MRA

SAR

DAR

CRA

CRB

4 bytes

MRB

MRA

SAR

DAR

CRA

CRB

Transfer information

for 2nd transfer round

in chain transfer

(4 longwords)

Chain transfer

Figure 4 Allocation of Transfer Information in Data Area

(2) Setting the DTC Vector Address

For each activation source, the DTC reads the start address of the transfer information from a vector table, then reads

the transfer information from this start address. Figure 5 shows the correspondence between the DTC vector table and

the transfer information.

For information on the correspondence between DTC activation sources and vector addresses, see the Data Transfer

Controller (DTC) section in the SH7137 Group Hardware Manual (RJJ09B0392).

Figure 5 Correspondence between DTC Vector Table and Transfer Information