SH7136/SH7137 Group

SCI Clock Synchronous Simultaneous Transmit and

Receive of Serial Data and DTC Data Transfer

REJ06B0890-0100/Rev.1.00

July 2009

Page 3 of 22

2. Description of the Sample Application

In this application example, the transmit data empty interrupt (TXI) and receive data full interrupt (RXI) of the serial

communication interface (SCI) are used to activate the data transfer controller (DTC) and perform clock synchronous

serial data simultaneous transmit and receive. The DTC is set to use two channels, one for SCI transmit and one for SCI

receive. The DTC’s normal transfer mode is used.

2.1

Operational Overview of Module Used

2.1.1

Serial Communication Interface (SCI)

The clock synchronous mode enables data transmit and receive operation in synchronization with a clock pulse, making

it suitable for high-speed serial communication. Either an internal clock or an external clock input via the SCK pin may

be selected as the clock source. When an internal clock is selected, the synchronization clock is output by the SCK pin.

When an external clock is selected, the synchronization clock is input to the SCK pin.

Internally, the SCI has independent transmit and receive blocks, and full-duplex communication is possible by using a

common synchronization clock. The transmit and receive blocks each have a double-buffered configuration, so data can

be read or written during transmission or reception, enabling continuous data transfer.

For details of the SCI, see the Serial Communication Interface (SCI) section in the SH7137 Group Hardware Manual

(RJJ09B0392).

Table 1 shows an overview of clock synchronous communication. Figure 2 is a block diagram of the SCI.

Table 1 Overview of Clock Synchronous Serial Communication

Item

Description

Number of channels

3 channels (SCI_0, SCI_1, SCI_2)

Clock sources

• Internal clock: Pφ, Pφ/4, Pφ/16, Pφ/64 (Pφ: peripheral clock)

• External clock: Clock input on SCK pin

Data format

• Transfer data length: 8-bit data fixed

• Transfer sequence: Selectable between LSB-first and MSB-first

Baud rate

• When internal clock selected: 250 bps to 5,000,000 bps (Pφ = 40 MHz

operation)

• When external clock selected: Max. 6,666,666.7 bps (Pφ = 40 MHz and

external clock input = 6.6667 MHz operation)

Receive error detection

Overrun error

Interrupt requests

• Transmit data empty interrupt (TXI)

• Transmit end interrupt (TEI)

• Receive data full interrupt (RXI)

• Receive error interrupt (ERI)

Clock source

• Selectable between internal clock and external clock

• When internal clock selected: Clock of SCI’s internal on-chip baud rate

generator is used for operation. Synchronization clock is output on SCK pin.

• When external clock selected: On-chip baud rate generator is not used.

External synchronization clock input via SCK pin is used for operation.