SH7136/SH7137 Group

SCI Clock Synchronous Simultaneous Transmit and

Receive of Serial Data and DTC Data Transfer

REJ06B0890-0100/Rev.1.00

July 2009

Page 13 of 22

2.4.3

Initialization of Data Transfer Controller (DTC)

Figure 10 shows the initial setting sequence for the data transfer controller (DTC).

[1]

Make vector table settings

[4]

[5]

[7]

[2]

[1] Operating mode selection

· RRS bit = B'0: No not skip reading DTC transfer information.

· RCHNE bit = B'0: Disable chain transfer after repeat transfer.

· ERR bit = B'0: Clear transfer stop flag.

DTC transfer information (DTC_RXI0) settings for SCI receive

[2] Operating mode A selection

· MD bit = B'00: Normal transfer mode

· Sz bit = B'00: Byte size transfer

· SM bit = B'00: SAR is fixed.

[3] Operating mode B selection

· CHNE bit = B'0: Disable chain transfer.

· DISEL bit = B'0: Enable interrupt after end of specified

transfer count.

· DM bit = B'10: Increment DAR after transfer.

[4] Transfer source address setting

Specify SCI receive data register_0 (SCRDR_0).

[5] Transfer destination address setting

Specify SCI receive data storage area (start address)

(on-chip RAM).

[6] Data transfer count: 32 times

[7] Specify block data transfer count (not used): 0 times

DTC transfer information (DTC_TXI0) settings for SCI transmit

[8] Operating mode A selection

· MD bit = B'00: Normal transfer mode

· Sz bit = B'00: Byte size transfer

· SM bit = B'10: Increment SAR after transfer.

[9] Operating mode B selection

· CHNE bit = B'0: Disable chain transfer.

· DISEL bit = B'0: Enable interrupt after end of transfer.

· DM bit = B'00: DAR is fixed.

[10] Transfer source address setting

Specify SCI transmit data storage area (start address)

(on-chip RAM).

[11] Transfer destination address setting

Specify SCI transmit data register_0 (SCTDR_0).

[12] Set data transfer count: 32 times

[13] Specify block data transfer count (not used): 0 times

[14] DTC vector base register setting

Allocate DTC vector table in on-chip RAM.

[15]

· Set DTC transfer information (DTC_RXI0) for SCI receive

in vector table.

· Set DTC transfer information (DTC_TXI0) for SCI transmit

in vector table.

[16] DTC interrupt vector settings

· Enable DTC activation by SCI_0 interrupt source RXI_0.

· Enable DTC activation by SCI_0 interrupt source TXI_0.

[3]

dtc_init()

END

Make settings in DTC control

register (DTCCR)

Make settings in DTC enable

register E (DTCERE)

DTC settings

for SCI

transmit

(DTC_TXI0)

DTC settings

for SCI receive

(DTC_RXI0)

Make setting in DTC vector base

register

[6]

[10]

[11]

[13]

[8]

[9]

[12]

[14]

[16]

[15]

Make setting in DTC transfer count

register A (CRA)

Make settings in DTC mode

register A (MRA)

Make settings in DTC mode

register B (MRB)

Make setting in DTC source

address register (SAR)

Make setting in DTC destination

address register (DAR)

Make setting in DTC transfer count

register B (CRB)

Make setting in DTC transfer count

register A (CRA)

Make settings in DTC mode

register A (MRA)

Make settings in DTC mode

register B (MRB)

Make setting in DTC source

address register (SAR)

Make setting in DTC destination

address register (DAR)

Make setting in DTC transfer count

register B (CRB)

Figure 10 Initialization of Data Transfer Controller (DTC)