14

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RESET Input (MAX7367/MAX7368)

The MAX7367/MAX7368 feature an active-low

RESET

input. When

RESET is driven low for more than 4ns, the

state machine to their default states, allowing a master

to recover from a bus fault condition.

Power-On Reset (POR)

holds the MAX7367/MAX7368/MAX7369 in a reset state

the reset condition is released, and the MAX7367/

initialized to their default states (all zeroes), causing all

the channels to be deselected.

Voltage Translation

The MAX7367/MAX7368/MAX7369 can be used as a volt-

age translator from the main bus to the extended buses.

For the MAX7367/MAX7368/MAX7369 to be used as a

than or equal to the lowest bus voltage.

patible, 2-wire serial interface consisting of a bidirec-

tional serial-data line (SDA) and a serial-clock line

(SCL). The master (typically a microcontroller) initiates

data transfer on the bus and generates the SCL.

Bit Transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable while SCL

is high (Figure 9).

Start and Stop Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, it issues a

STOP (P) condition by transitioning the SDA from low to

high while SCL is high. The bus is then free for another

transmission (Figure 10).

Acknowledge Bit

Successful data transfers are acknowledged with an

acknowledge bit (A) or a not-acknowledge bit (NA).

Both the master and the MAX7367/MAX7368/MAX7369

(slave) generate acknowledge bits. To generate an

acknowledge, the receiving device must pull SDA low

before the rising edge of the acknowledge-related

clock pulse (ninth pulse) and keep it low during the

high period of the clock pulse (Figure 11). In the case

of an unsuccessful data transfer, the receiver allows

SDA to be pulled high before the rising edge of the

acknowledge-related clock pulse and leaves it high

during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer happens if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the master should reattempt com-

munication at a later time.

SDA

SCL

DATA STABLE

DATA VALID

CHANGE OF

DATA ALLOWED

Figure 9. Bit Transfer

SDA

SCL

S

P

START

CONDITION

STOP

CONDITION

Figure 10. Start and Stop Conditions

CLOCK PULSE FOR

ACKNOWLEDGMENT

NOT ACKNOWLEDGE

ACKNOWLEDGE

12

8

9

SDA

SCL

START

CONDITION

Figure 11. Acknowledge