16-Bit Mixed-Signal Microcontroller

with LCD Interface

8

_______________________________________________________________________________________

Note 12: Programming time does not include overhead associated with the utility ROM interface.

Note 14: The operational input voltage range for each individual input of a differentially configured pair is from GND to AVDD. The

Note 15: The typical value is applied when a conversion is requested with ADPMO = 0. Under these conditions, the minimum delay

is met. If ADPMO = 1, the user is responsible for ensuring the 4µs delay time is met.

Note 16: Switching ADC reference from either internal or external reference to AVDD. Sample accuracy is not guaranteed prior to

ADC reference settlement.

Note 17: Total on-board decoupling capacitance on the AVDD pin < 100nF. The output impedance of the regulator driving the

AVDD pin < 10

Ω.

Note 18: This parameter is guaranteed by design and is not production tested.

RECOMMENDED DC OPERATING CONDITIONS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SPI (See Figures 1 and 2)

SPI Master Operating Frequency

MHz

SPI Slave Operating Frequency

MHz

SCLK Output Pulse-Width

High/Low

- 25

ns

SCLK Input Pulse-Width

High/Low

ns

MOSI Output Hold Time After

SCLK Sample Edge

- 25

ns

MOSI Output Valid to Sample

Edge

- 25

ns

MISO Input Valid to SCLK

Sample Edge Rise/Fall Setup

25

ns

MISO Input to SCLK Sample

Edge Rise/Fall Hold

0

ns

SCLK Inactive to MOSI Inactive

- 25

ns

SSEL Active to First Shift Edge

ns

MOSI Input to SCLK Sample

Edge Rise/Fall Setup

20

ns

MOSI Input from SCLK Sample

Edge Transition Hold

25

ns

MISO Output Valid After SCLK

Shift Edge Transition

25

ns

SSEL Inactive

25

ns

SCLK Inactive to SSEL Rising

25

ns

MISO Output Disabled After

SSEL Edge Rise

50

ns