MAXQ2010-RFX+ datasheet(27/34 Pages) MAXIM

27 / 34 page

16-Bit Mixed-Signal Microcontroller

with LCD Interface

______________________________________________________________________________________

ranges from 0000h to the value stored in the 16-bit cap-

ture/reload register (TBR), whereas in other implemen-

tations (e.g., Timer 1) the count ranges from the value

in the reload register to FFFFh. These timers are fully

described in the

MAXQ Family User’s Guide.

Timer B operational modes include the following:

• Autoreload

• Autoreload Using External Pin

• Capture Using External Pin

• Up/Down Count Using External Pin

• Up-Count PWM/Output

• Up/Down PWM/Output

• Clock Output on TBB Pin

Watchdog Timer

An internal watchdog timer greatly increases system reli-

ability. The timer resets the device if software execution

is disturbed. The watchdog timer is a free-running

counter designed to be periodically reset by the applica-

tion software. If software is operating correctly, the

counter is periodically reset and never reaches its maxi-

mum count. However, if software operation is interrupted,

the timer does not reset, triggering a system reset and

optionally a watchdog timer interrupt. This protects the

system against electrical noise or electrostatic discharge

(ESD) upsets that could cause uncontrolled processor

operation. The internal watchdog timer is an upgrade to

older designs with external watchdog devices, reducing

system cost and simultaneously increasing reliability.

The watchdog timer is controlled through bits in the

WDCN register. Its timeout period can be set to one of

four programmable intervals ranging from 212 to 221

system clocks in its default mode, allowing flexibility to

support different types of applications. The interrupt

occurs 512 system clocks before the reset, allowing the

system to execute an interrupt and place the system in

a known, safe state before the device performs a total

system reset. At 8MHz, watchdog timeout periods can

be programmed from 512µs to 67s, depending on the

system clock mode.

Hardware Multiplier

The internal hardware multiplier supports high-speed

multiplications. The multiplier can complete a 16-bit x

16-bit multiply-and-accumulate/subtract operation in a

single cycle with the support of a 48-bit accumulator.

The multiplier is a fixed-point arithmetic unit. The

operands can be either signed or unsigned numbers,

but the data type must be defined by the application

software prior to loading the operand registers.

Seven different multiply operations can be performed

without requiring direct intervention of the microcon-

troller core. These include the following:

• Unsigned 16-bit multiplication

• Unsigned 16-bit multiplication and accumulation

• Unsigned 16-bit multiplication and subtraction

• Signed 16-bit multiplication

• Signed 16-bit multiplication and negate

• Signed 16-bit multiplication and accumulation

• Signed 16-bit multiplication and subtraction

Each of these operations is controlled and accessed

through six SFR registers. The 8-bit multiplier control

operand count, optional hardware-based square func-

tion, write option on the MC register, the overflow flag,

and the clear control for operand registers and accu-

mulator. Loading and unloading of the data is achieved

through five 16-bit SFR registers.

Only one cycle is needed for computation. This means

that the result of an operation is ready in the next cycle

immediately following the loading of the last operand.

Back-to-back operations can be performed without wait

states between operations, independent of data type

and operand count.

Analog-to-Digital Converter

The MAXQ2010 contains a 12-bit successive approxi-

mation analog-to-digital converter (ADC) with an analog

mux (Figure 7). The mux selects the ADC input from

eight single-ended channels or four differential chan-

nels. An internal precision bandgap reference can be

used for the ADC reference voltage, or the reference

voltage can be externally driven. Additionally, the ana-

log supply voltage (AVDD) can also be used as the

voltage reference. The ADC runs off a 2.7V to 3.6V

power supply and at a conversion rate up to 300ksps.

The ADC block includes a 12-bit SAR core, ADC con-

trols, a reference generator, and a circular block of six-

teen 12-bit data buffers. The ADC is controlled by SFR

registers. An autoscan feature allows the user to select

up to eight sampling channels for storage in the 16

memory locations.

There are two conversion modes: single-sequence

mode and continuous-sequence mode.

The ADC’s internal power-management system auto-

matically powers down when the conversion(s) are

done (ADCONV = 0). The start conversion bit,

ADCONV, is used to start all conversion processes. If

the ADC power-management override bit is cleared

MAXQ2010-RFX+ Datasheet(PDF) 27 Page - Maxim Integrated Products

MAXQ2010-RFX+ Datasheet(HTML) 27 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL