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MAXQ2010-RFX+ Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAXQ2010-RFX+ Datasheet(HTML) 11 Page - Maxim Integrated Products |
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11 / 34 page ![]() 16-Bit Mixed-Signal Microcontroller with LCD Interface ______________________________________________________________________________________ 11 I2C BUS CONTROLLER TIMING (VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 22) (Figure 4) STANDARD MODE FAST MODE PARAMETER SYMBOL MIN MAX MIN MAX UNITS Operating Frequency fI2C 0 100 0 400 kHz Hold Time After (Repeated) START tHD:STA 4.0 0.6 μs Clock Low Period tLOW_I2C 4.7 1.3 μs Clock High Period tHIGH_I2C 4.0 0.6 μs Setup Time for Repeated START tSU:STA 4.7 0.6 μs Hold Time for Data tHD:DAT 0 (Note 23) 3.45 (Note 24) 0 (Note 23) 0.9 (Note 24) μs Setup Time for Data tSU:DAT 250 100 (Note 25) ns SDA/SCL Fall Time tF_I2C 300 20 + 0.1CB (Note 26) 300 ns SDA/SCL Rise Time tR_I2C 1000 20 + 0.1CB (Note 26) 300 ns Setup Time for STOP tSU:STO 4.0 0.6 μs Bus-Free Time Between STOP and START tBUF 4.7 1.3 μs Capacitive Load for Each Bus Line CB 400 400 pF Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) VNL_I2C 0.1 x VDVDD 0.1 x VDVDD V Noise Margin at the High Level for Each Connected Device (Including Hysteresis) VNH_I2C 0.2 x VDVDD 0.2 x VDVDD V Note 22: All values referenced to VIH_I2C(MIN) and VIL_I2C(MAX). Note 23: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH_I2C(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 24: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW_I2C) of the SCL signal. Note 25: A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU:DAT ≥ 250ns must be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR_I2C(MAX) + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode I2C specification) before the SCL line is released. Note 26: CB—Total capacitance of one bus line in pF. |
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